Silicon Laboratories SI5326 Manuel d'utilisateur

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Confidential Rev. 0.2 2/07 Copyright © 2007 by Silicon Laboratories Si5326
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5326
PRELIMINARY DATA SHEET
ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR
Description
The Si5326 is a jitter-attenuating precision clock multiplier for
applications requiring sub 1 ps jitter performance. The Si5326
accepts dual clock inputs ranging from 2 kHz to 710 MHz and
generates two clock outputs ranging from 2 kHz to 945 MHz
and select frequencies to 1.4 GHz. The two outputs are
divided down separately from a common source. The device
provides virtually any frequency translation combination
across this operating range. The Si5326 input clock
frequency and clock multiplication ratio are programmable
through an I
2
C or SPI interface. The Si5326 is based on
Silicon Laboratories' 3rd-generation DSPLL
®
technology,
which provides any-rate frequency synthesis and jitter
attenuation in a highly integrated PLL solution that eliminates
the need for external VCXO and loop filter components. The
DSPLL loop bandwidth is digitally programmable, providing
jitter performance optimization at the application level.
Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5326
is ideal for providing clock multiplication and jitter attenuation
in high performance timing applications.
Applications
SONET/SDH OC-48/OC-192 line cards
GbE/10GbE, 1/2/4/8/10GFC line cards
ITU G.709 and custom FEC line cards
Optical modules
Wireless basestations
Data converter clocking
xDSL
SONET/SDH + PDH clock synthesis
Test and measurement
Features
Generates any frequency from 2 kHz to 945 MHz
and select frequencies to 1.4 GHz from an input
frequency of 2 kHz to 710 MHz
Ultra-low jitter clock outputs w/jitter generation as
low as 0.3ps rms (50kHz80MHz)
Integrated loop filter with selectable loop bandwidth
(60Hz to 8.4kHz)
Meets OC-192 GR-253-CORE jitter specifications
Dual clock inputs w/manual or automatically
controlled hitless switching
Dual clock outputs with selectable signal format
(LVPECL, LVDS, CML, CMOS)
Support for ITU G.709 and custom FEC ratios
(255/238, 255/237, 255/236)
LOL, LOS, FOS alarm outputs
Digitally-controlled output phase adjust
I
2
C or SPI programmable
On-chip voltage regulator for 1.8, 2.5, or 3.3 V
±10% operation
Small size: 6 x 6 mm 36-lead QFN
Pb-free, ROHS compliant
DSPLL
®
Loss of Signal/
Frequency Offset
Xtal or Refclock
CKOUT2
CKIN1
CKOUT1
CKIN2
÷ N31
÷ N2
÷ NC1
÷ NC2
Latency Control
Signal Detect
Device Interrupt
VDD (1.8, 2.5, or 3.3 V)
GND
÷ N32
Loss of Lock
Clock Select
I
2
C/SPI Port
Control
Rate Select
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1 2 3 4 5 6 ... 15 16

Résumé du contenu

Page 1 - Xtal or Refclock

Confidential Rev. 0.2 2/07 Copyright © 2007 by Silicon Laboratories Si5326This information applies to a product under development. Its characteristics

Page 2

Si532610 Confidential Rev. 0.223 SDA_SDO I/O LVCMOS Serial Data.In I2C control mode (CMODE = 0), this pin functions as the bidirec-tional serial data

Page 3

Si5326Confidential Rev. 0.2 113. Ordering GuideOrdering Part NumberOutput Clock Frequency RangePackage Temperature RangeSi5326A-B-GM 2 kHz–945 MHz970

Page 4 - Typical Phase Noise Plot

Si532612 Confidential Rev. 0.24. Package Outline: 36-Pin QFNFigure 4 illustrates the package details for the Si5326. Table 3 lists the values for the

Page 5 - C Control Mode)

Si5326Confidential Rev. 0.2 135. Recommended PCB LayoutFigure 5. PCB Land Pattern Diagram

Page 6 - 1. Functional Description

Si532614 Confidential Rev. 0.2Table 4. PCB Land Pattern DimensionsDimension MIN MAXe 0.50 BSC.E5.42 REF.D5.42 REF.E2 4.00 4.20D2 4.00 4.20GE 4.53 —GD

Page 7 - 2. Pin Descriptions: Si5326

Si5326Confidential Rev. 0.2 15DOCUMENT CHANGE LISTRevision 0.1 to Revision 0.2 Updated LVTTL to LVCMOS is Table 2, “Absolute Maximum Ratings,” on pag

Page 8 - 8 Confidential Rev. 0.2

Si532616 Confidential Rev. 0.2CONTACT INFORMATIONSilicon Laboratories Inc.400 West Cesar ChavezAustin, TX 78701Tel: 1+(512) 416-8500Fax: 1+(512) 416-9

Page 9 - Confidential Rev. 0.2 9

Si53262 Confidential Rev. 0.2Table 1. Performance Specifications (VDD= 1.8, 2.5, or 3.3 V ±10%, TA= –40 to 85 ºC)Parameter Symbol Test Condition Min T

Page 10 - 10 Confidential Rev. 0.2

Si5326Confidential Rev. 0.2 3Duty Cycle CKODC 45 — 55 %PLL PerformanceJitter Generation JGENfOUT = 622.08 MHz,LVPECL output format50 kHz–80 MHz— 0.3 T

Page 11 - 3. Ordering Guide

Si53264 Confidential Rev. 0.2Figure 1. Typical Phase Noise Plot155.52 MHz in, 622.08 MHz out-160-140-120-100-80-60-40-200100 1000 10000 100000 1000000

Page 12 - Table 3. Package Dimensions

Si5326Confidential Rev. 0.2 5Figure 2. Si5326 Typical Application Circuit (I2C Control Mode)Figure 3. Si5326 Typical Application Circuit (SPI Control

Page 13 - 5. Recommended PCB Layout

Si53266 Confidential Rev. 0.21. Functional DescriptionThe Si5326 is a jitter-attenuating precision clockmultiplier for applications requiring sub 1 p

Page 14

Si5326Confidential Rev. 0.2 72. Pin Descriptions: Si5326Pin numbers are preliminary and subject to change.Pin # Pin Name I/O Signal Level Description

Page 15 - DOCUMENT CHANGE LIST

Si53268 Confidential Rev. 0.24C2BOLVCMOSCKIN2 Invalid Indicator.This pin functions as a LOS (and optionally FOS) alarm indicator for CKIN2 if CK2_BAD_

Page 16 - CONTACT INFORMATION

Si5326Confidential Rev. 0.2 919 DEC I LVCMOS Latency Decrement.A pulse on this pin decreases the input to output device latency by 1/fOSC (approximate

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