Silicon Laboratories C8051F340 Manuel d'utilisateur

Full Speed USB Flash MCU FamilyC8051F340/1/2/3/4/5/6/7Rev. 0.5 1/06 Copyright © 2006 by Silicon Laboratories C8051F34xThis information applies to a pr

C8051F340/1/2/3/4/5/6/710 Rev. 0.58. Voltage Regulator (REG0)Table 8.1. Voltage Regulator Electrical Specifications...

C8051F340/1/2/3/4/5/6/7100 Rev. 0.5NOTES:

Rev. 0.5 101C8051F340/1/2/3/4/5/6/711. Reset SourcesReset circuitry allows the controller to be easily placed in a predefined default condition. On en

C8051F340/1/2/3/4/5/6/7102 Rev. 0.511.1. Power-On ResetDuring power-up, the device is held in a reset state and the /RST pin is driven low until VDD s

Rev. 0.5 103C8051F340/1/2/3/4/5/6/711.2. Power-Fail Reset / VDD MonitorWhen a power-down transition or power irregularity causes VDD to drop below VRS

C8051F340/1/2/3/4/5/6/7104 Rev. 0.511.3. External ResetThe external /RST pin provides a means for external circuitry to force the device into a reset

Rev. 0.5 105C8051F340/1/2/3/4/5/6/711.8. Software ResetSoftware may force a reset by writing a ‘1’ to the SWRSF bit (RSTSRC.4). The SWRSF bit will rea

C8051F340/1/2/3/4/5/6/7106 Rev. 0.5SFR Definition 11.2. RSTSRC: Reset SourceBit7: USBRSF: USB Reset Flag0: Read: Last reset was not a USB reset; Write

Rev. 0.5 107C8051F340/1/2/3/4/5/6/7Table 11.1. Reset Electrical Characteristics–40 to +85 °C unless otherwise specified.Parameter Conditions Min Typ M

C8051F340/1/2/3/4/5/6/7108 Rev. 0.5NOTES:

Rev. 0.5 109C8051F340/1/2/3/4/5/6/712. Flash MemoryOn-chip, re-programmable Flash memory is included for program code and non-volatile data storage. T

Rev. 0.5 11C8051F340/1/2/3/4/5/6/7Figure 16.2. USB0 Register Access Scheme... 166Table 16.2. USB

C8051F340/1/2/3/4/5/6/7110 Rev. 0.512.1.3. Flash Write ProcedureBytes in Flash memory can be written one byte at a time, or in groups of two. The FLBW

Rev. 0.5 111C8051F340/1/2/3/4/5/6/712.2. Non-volatile Data StorageThe Flash memory can be used for non-volatile data storage as well as program code.

C8051F340/1/2/3/4/5/6/7112 Rev. 0.5Figure 12.1. Flash Program Memory Map and Security ByteAccess limit set according to the FLASH security lock byteC8

Rev. 0.5 113C8051F340/1/2/3/4/5/6/7The level of FLASH security depends on the FLASH access method. The three FLASH access methods that can be restrict

C8051F340/1/2/3/4/5/6/7114 Rev. 0.5SFR Definition 12.1. PSCTL: Program Store R/W ControlSFR Definition 12.2. FLKEY: Flash Lock and KeyBits7–3: Unused:

Rev. 0.5 115C8051F340/1/2/3/4/5/6/7SFR Definition 12.3. FLSCL: Flash ScaleBits7: FOSE: Flash One-shot EnableThis bit enables the Flash read one-shot.

C8051F340/1/2/3/4/5/6/7116 Rev. 0.5NOTES:

Rev. 0.5 117C8051F340/1/2/3/4/5/6/713. External Data Memory Interface and On-Chip XRAM4k Bytes (C8051F340/2/4/6) or 2k Bytes (C8051F341/3/5/7) of RAM

C8051F340/1/2/3/4/5/6/7118 Rev. 0.513.2. Accessing USB FIFO SpaceThe C8051F340/1/2/3/4/5/6/7 include 1k of RAM which functions as USB FIFO space. Figu

Rev. 0.5 119C8051F340/1/2/3/4/5/6/713.3. Configuring the External Memory InterfaceConfiguring the External Memory Interface consists of five steps:1.

C8051F340/1/2/3/4/5/6/712 Rev. 0.5Figure 20.10. SPI Slave Timing (CKPHA = 0)... 240Figure 20.11.

C8051F340/1/2/3/4/5/6/7120 Rev. 0.5SFR Definition 13.1. EMI0CN: External Memory Interface ControlBits7–0: PGSEL[7:0]: XRAM Page Select Bits.The XRAM P

Rev. 0.5 121C8051F340/1/2/3/4/5/6/7SFR Definition 13.2. EMI0CF: External Memory ConfigurationBit7: Unused. Read = 0b. Write = don’t care.Bit6: USBFAE:

C8051F340/1/2/3/4/5/6/7122 Rev. 0.513.5. Multiplexed and Non-multiplexed SelectionThe External Memory Interface is capable of acting in a Multiplexed

Rev. 0.5 123C8051F340/1/2/3/4/5/6/713.5.2. Non-multiplexed ConfigurationIn Non-multiplexed mode, the Data Bus and the Address Bus pins are not shared.

C8051F340/1/2/3/4/5/6/7124 Rev. 0.513.6.1. Internal XRAM OnlyWhen EMI0CF.[3:2] are set to ‘00’, all MOVX instructions will target the internal XRAM sp

Rev. 0.5 125C8051F340/1/2/3/4/5/6/713.6.3. Split Mode with Bank SelectWhen EMI0CF.[3:2] are set to ‘10’, the XRAM memory map is split into two areas,

C8051F340/1/2/3/4/5/6/7126 Rev. 0.5SFR Definition 13.3. EMI0TC: External Memory Timing ControlBits7–6: EAS1–0: EMIF Address Setup Time Bits.00: Addres

Rev. 0.5 127C8051F340/1/2/3/4/5/6/713.7.1. Non-multiplexed Mode13.7.1.1.16-bit MOVX: EMI0CF[4:2] = ‘101’, ‘110’, or ‘111’.Figure 13.5. Non-multiplexed

C8051F340/1/2/3/4/5/6/7128 Rev. 0.513.7.1.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘101’ or ‘111’.Figure 13.6. Non-multiplexed 8-bit MOVX witho

Rev. 0.5 129C8051F340/1/2/3/4/5/6/713.7.1.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘110’.Figure 13.7. Non-multiplexed 8-bit MOVX with Bank Select

Rev. 0.5 13C8051F340/1/2/3/4/5/6/7List of RegistersSFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select . . . . . . . . . . . . . . . . . . . 48S

C8051F340/1/2/3/4/5/6/7130 Rev. 0.513.7.2. Multiplexed Mode13.7.2.1.16-bit MOVX: EMI0CF[4:2] = ‘001’, ‘010’, or ‘011’.Figure 13.8. Multiplexed 16-bit

Rev. 0.5 131C8051F340/1/2/3/4/5/6/713.7.2.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘001’ or ‘011’.Figure 13.9. Multiplexed 8-bit MOVX without B

C8051F340/1/2/3/4/5/6/7132 Rev. 0.513.7.2.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘010’.Figure 13.10. Multiplexed 8-bit MOVX with Bank Select Tim

Rev. 0.5 133C8051F340/1/2/3/4/5/6/7Table 13.1. AC Parameters for External Memory InterfaceParameter Description Min* Max* UnitsTACSAddress / Control S

C8051F340/1/2/3/4/5/6/7134 Rev. 0.5NOTES:

Rev. 0.5 135C8051F340/1/2/3/4/5/6/714. OscillatorsC8051F340/1/2/3/4/5/6/7 devices include a programmable internal high-frequency oscillator, a program

C8051F340/1/2/3/4/5/6/7136 Rev. 0.514.1. Programmable Internal High-Frequency (H-F) OscillatorAll C8051F340/1/2/3/4/5/6/7 devices include a programmab

Rev. 0.5 137C8051F340/1/2/3/4/5/6/7SFR Definition 14.2. OSCICL: Internal H-F Oscillator Calibration14.2. Programmable Internal Low-Frequency (L-F) Osc

C8051F340/1/2/3/4/5/6/7138 Rev. 0.5SFR Definition 14.3. OSCLCN: Internal L-F Oscillator ControlBit7: OSCLEN: Internal L-F Oscillator Enable.0: Interna

Rev. 0.5 139C8051F340/1/2/3/4/5/6/714.3. External Oscillator Drive CircuitThe external oscillator circuit may drive an external crystal, ceramic reson

C8051F340/1/2/3/4/5/6/714 Rev. 0.5SFR Definition 14.3. OSCLCN: Internal L-F Oscillator Control . . . . . . . . . . . . . . . . . . 138SFR Definition 1

C8051F340/1/2/3/4/5/6/7140 Rev. 0.514.3.3. External RC ExampleIf an RC network is used as an external oscillator source for the MCU, the circuit shoul

Rev. 0.5 141C8051F340/1/2/3/4/5/6/7SFR Definition 14.4. OSCXCN: External Oscillator ControlBit7: XTLVLD: Crystal Oscillator Valid Flag.(Read only when

C8051F340/1/2/3/4/5/6/7142 Rev. 0.514.4. 4x Clock MultiplierThe 4x Clock Multiplier allows a 12 MHz oscillator to generate the 48 MHz clock required f

Rev. 0.5 143C8051F340/1/2/3/4/5/6/714.5. System and USB Clock SelectionThe internal oscillator requires little start-up time and may be selected as th

C8051F340/1/2/3/4/5/6/7144 Rev. 0.5SFR Definition 14.6. CLKSEL: Clock SelectBit 7: Unused. Read = 0b; Write = don’t care.Bits6–4: USBCLK2–0: USB Clock

Rev. 0.5 145C8051F340/1/2/3/4/5/6/7Table 14.1. Oscillator Electrical CharacteristicsVDD = 2.7 to 3.6 V; –40 to +85 °C unless otherwise specifiedParame

C8051F340/1/2/3/4/5/6/7146 Rev. 0.5NOTES:

Rev. 0.5 147C8051F340/1/2/3/4/5/6/715. Port Input/OutputDigital and analog resources are available through 40 I/O pins (C8051F340/1/4/5) or 25 I/O pin

C8051F340/1/2/3/4/5/6/7148 Rev. 0.5Figure 15.2. Port I/O Cell Block DiagramGND/PORT-OUTENABLEPORT-OUTPUTPUSH-PULLVDDVDD/WEAK-PULLUP(WEAK)PORTPADANALOG

Rev. 0.5 149C8051F340/1/2/3/4/5/6/715.1. Priority Crossbar DecoderThe Priority Crossbar Decoder (Figure 15.3) assigns a priority to each I/O function,

Rev. 0.5 15C8051F340/1/2/3/4/5/6/7USB Register Definition 16.20. EINCSRH: USB0 IN Endpoint Control High Byte . . . 187USB Register Definition 16.21.

C8051F340/1/2/3/4/5/6/7150 Rev. 0.5Figure 15.4. Crossbar Priority Decoder with Crystal Pins SkippedRegisters XBR0, XBR1, and XBR2 are used to assign t

Rev. 0.5 151C8051F340/1/2/3/4/5/6/715.2. Port I/O InitializationPort I/O initialization consists of the following steps:Step 1. Select the input mode

C8051F340/1/2/3/4/5/6/7152 Rev. 0.5SFR Definition 15.1. XBR0: Port I/O Crossbar Register 0Bit7: CP1AE: Comparator1 Asynchronous Output Enable0: Asynch

Rev. 0.5 153C8051F340/1/2/3/4/5/6/7SFR Definition 15.2. XBR1: Port I/O Crossbar Register 1SFR Definition 15.3. XBR2: Port I/O Crossbar Register 2Bit7:

C8051F340/1/2/3/4/5/6/7154 Rev. 0.515.3. General Purpose Port I/OPort pins that remain unassigned by the Crossbar and are not used by analog periphera

Rev. 0.5 155C8051F340/1/2/3/4/5/6/7SFR Definition 15.6. P0MDOUT: Port0 Output Mode SFR Definition 15.7. P0SKIP: Port0 SkipBits7–0: Output Configuratio

C8051F340/1/2/3/4/5/6/7156 Rev. 0.5SFR Definition 15.8. P1: Port1 LatchSFR Definition 15.9. P1MDIN: Port1 Input ModeSFR Definition 15.10. P1MDOUT: Por

Rev. 0.5 157C8051F340/1/2/3/4/5/6/7SFR Definition 15.11. P1SKIP: Port1 SkipSFR Definition 15.12. P2: Port2 LatchSFR Definition 15.13. P2MDIN: Port2 In

C8051F340/1/2/3/4/5/6/7158 Rev. 0.5SFR Definition 15.14. P2MDOUT: Port2 Output ModeSFR Definition 15.15. P2SKIP: Port2 SkipBits7–0: Output Configurati

Rev. 0.5 159C8051F340/1/2/3/4/5/6/7SFR Definition 15.16. P3: Port3 LatchSFR Definition 15.17. P3MDIN: Port3 Input ModeSFR Definition 15.18. P3MDOUT: P

C8051F340/1/2/3/4/5/6/716 Rev. 0.5C2 Register Definition 23.2. DEVICEID: C2 Device ID . . . . . . . . . . . . . . . . . . . . . . . . 279C2 Register D

C8051F340/1/2/3/4/5/6/7160 Rev. 0.5SFR Definition 15.19. P3SKIP: Port3 SkipSFR Definition 15.20. P4: Port4 LatchBits7–0: P3SKIP[3:0]: Port3 Crossbar S

Rev. 0.5 161C8051F340/1/2/3/4/5/6/7SFR Definition 15.21. P4MDIN: Port4 Input ModeSFR Definition 15.22. P4MDOUT: Port4 Output ModeBits7–0: Analog Input

C8051F340/1/2/3/4/5/6/7162 Rev. 0.5 Table 15.1. Port I/O DC Electrical CharacteristicsVDD = 2.7 to 3.6 V, –40 to +85 °C unless otherwise specifiedPar

Rev. 0.5 163C8051F340/1/2/3/4/5/6/716. Universal Serial Bus Controller (USB0)C8051F340/1/2/3/4/5/6/7 devices include a complete Full/Low Speed USB fun

C8051F340/1/2/3/4/5/6/7164 Rev. 0.516.1. Endpoint AddressingA total of eight endpoint pipes are available. The control endpoint (Endpoint0) always fun

Rev. 0.5 165C8051F340/1/2/3/4/5/6/7SFR Definition 16.1. USB0XCN: USB0 Transceiver ControlBit7: PREN: Internal Pull-up Resistor EnableThe location of t

C8051F340/1/2/3/4/5/6/7166 Rev. 0.516.3. USB Register AccessThe USB0 controller registers listed in Table 16.2 are accessed through two SFRs: USB0 Add

Rev. 0.5 167C8051F340/1/2/3/4/5/6/7SFR Definition 16.2. USB0ADR: USB0 Indirect AddressBits7: BUSY: USB0 Register Read Busy FlagThis bit is used durin

C8051F340/1/2/3/4/5/6/7168 Rev. 0.5SFR Definition 16.3. USB0DAT: USB0 DataThis SFR is used to indirectly read and write USB0 registers. Write Procedur

Rev. 0.5 169C8051F340/1/2/3/4/5/6/7USB Register Definition 16.4. INDEX: USB0 Endpoint IndexTable 16.2. USB0 Controller Registers USB Register NameUSB

Rev. 0.5 17C8051F340/1/2/3/4/5/6/71. System OverviewC8051F340/1/2/3/4/5/6/7 devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlight

C8051F340/1/2/3/4/5/6/7170 Rev. 0.516.4. USB Clock ConfigurationUSB0 is capable of communication as a Full or Low Speed USB function. Communication sp

Rev. 0.5 171C8051F340/1/2/3/4/5/6/716.5. FIFO Management1024 bytes of on-chip XRAM are used as FIFO space for USB0. This FIFO space is split between E

C8051F340/1/2/3/4/5/6/7172 Rev. 0.516.5.2. FIFO Double BufferingFIFO slots for Endpoints1-3 can be configured for double-buffered mode. In this mode,

Rev. 0.5 173C8051F340/1/2/3/4/5/6/716.6. Function AddressingThe FADDR register holds the current USB0 function address. Software should write the host

C8051F340/1/2/3/4/5/6/7174 Rev. 0.5“14. Oscillators” on page 135 for more details on internal oscillator configuration, including the Suspend mode fea

Rev. 0.5 175C8051F340/1/2/3/4/5/6/7USB Register Definition 16.8. POWER: USB0 PowerBit7: ISOUD: ISO UpdateThis bit affects all IN Isochronous endpoints

C8051F340/1/2/3/4/5/6/7176 Rev. 0.5USB Register Definition 16.9. FRAMEL: USB0 Frame Number LowUSB Register Definition 16.10. FRAMEH: USB0 Frame Number

Rev. 0.5 177C8051F340/1/2/3/4/5/6/7USB Register Definition 16.11. IN1INT: USB0 IN Endpoint Interrupt USB Register Definition 16.12. OUT1INT: USB0 Out

C8051F340/1/2/3/4/5/6/7178 Rev. 0.5USB Register Definition 16.13. CMINT: USB0 Common InterruptBits7–4: Unused. Read = 0000b; Write = don’t care.Bit3:

Rev. 0.5 179C8051F340/1/2/3/4/5/6/7USB Register Definition 16.14. IN1IE: USB0 IN Endpoint Interrupt EnableUSB Register Definition 16.15. OUT1IE: USB0

C8051F340/1/2/3/4/5/6/718 Rev. 0.5Table 1.1. Product Selection GuideOrdering Part NumberMIPS (Peak)Flash Memory (Bytes)RAMCalibrated Internal Oscillat

C8051F340/1/2/3/4/5/6/7180 Rev. 0.5USB Register Definition 16.16. CMIE: USB0 Common Interrupt Enable16.9. The Serial Interface EngineThe Serial Interf

Rev. 0.5 181C8051F340/1/2/3/4/5/6/7The E0CNT register (USB Register Definition 16.18) holds the number of received data bytes in the Endpoint0 FIFO. H

C8051F340/1/2/3/4/5/6/7182 Rev. 0.516.10.3.Endpoint0 OUT TransactionsWhen a SETUP request is received that requires the host to transmit data to USB0,

Rev. 0.5 183C8051F340/1/2/3/4/5/6/7USB Register Definition 16.17. E0CSR: USB0 Endpoint0 ControlBit7: SSUEND: Serviced Setup EndWrite: Software should

C8051F340/1/2/3/4/5/6/7184 Rev. 0.5USB Register Definition 16.18. E0CNT: USB0 Endpoint 0 Data Count16.11. Configuring Endpoints1-3 Endpoints1-3 are co

Rev. 0.5 185C8051F340/1/2/3/4/5/6/7Writing ‘1’ to INPRDY without writing any data to the endpoint FIFO will cause a zero-length packet to be transmitt

C8051F340/1/2/3/4/5/6/7186 Rev. 0.5USB Register Definition 16.19. EINCSRL: USB0 IN Endpoint Control Low ByteBit7: Unused. Read = 0; Write = don’t care

Rev. 0.5 187C8051F340/1/2/3/4/5/6/7USB Register Definition 16.20. EINCSRH: USB0 IN Endpoint Control High Byte16.13. Controlling Endpoints1-3 OUTEndpoi

C8051F340/1/2/3/4/5/6/7188 Rev. 0.5A Bulk or Interrupt pipe can be shut down (or Halted) by writing ‘1’ to the SDSTL bit (EOUTCSRL.5). While SDSTL = ‘

Rev. 0.5 189C8051F340/1/2/3/4/5/6/7USB Register Definition 16.21. EOUTCSRL: USB0 OUT Endpoint Control Low Byte Bit7: CLRDT: Clear Data ToggleWrite: So

Rev. 0.5 19C8051F340/1/2/3/4/5/6/7Figure 1.1. C8051F340/1/4/5 Block DiagramAnalog Peripherals10-bit 200ksps ADCAMUXTemp Sensor2 Comparators+-VREFVDDCP

C8051F340/1/2/3/4/5/6/7190 Rev. 0.5USB Register Definition 16.22. EOUTCSRH: USB0 OUT Endpoint Control High ByteUSB Register Definition 16.23. EOUTCNTL

Rev. 0.5 191C8051F340/1/2/3/4/5/6/7 Table 16.4. USB Transceiver Electrical CharacteristicsVDD = 3.0 to 3.6 V, –40 to +85 °C unless otherwise specifie

C8051F340/1/2/3/4/5/6/7192 Rev. 0.5NOTES:

Rev. 0.5 193C8051F340/1/2/3/4/5/6/717. SMBusThe SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System M

C8051F340/1/2/3/4/5/6/7194 Rev. 0.517.1. Supporting DocumentsIt is assumed the reader is familiar with or has access to the following supporting docum

Rev. 0.5 195C8051F340/1/2/3/4/5/6/7The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set t

C8051F340/1/2/3/4/5/6/7196 Rev. 0.517.3.2. Clock Low ExtensionSMBus provides a clock synchronization mechanism, similar to I2C, which allows devices w

Rev. 0.5 197C8051F340/1/2/3/4/5/6/7SMBus configuration options include:• Timeout detection (SCL Low Timeout and/or Bus Free Timeout)• SDA setup and ho

C8051F340/1/2/3/4/5/6/7198 Rev. 0.517.4.1. SMBus Configuration RegisterThe SMBus Configuration register (SMB0CF) is used to enable the SMBus Master an

Rev. 0.5 199C8051F340/1/2/3/4/5/6/7Figure 17.4 shows the typical SCL generation described by Equation 17.2. Notice that THIGH is typically twice as la

C8051F340/1/2/3/4/5/6/72 Rev. 0.5NOTES:

C8051F340/1/2/3/4/5/6/720 Rev. 0.5Figure 1.2. C8051F342/3/6/7 Block DiagramAnalog Peripherals10-bit 200 ksps ADCAMUXTemp Sensor2 Comparators+-VREFVDDC

C8051F340/1/2/3/4/5/6/7200 Rev. 0.5SFR Definition 17.1. SMB0CF: SMBus Clock/ConfigurationBit7: ENSMB: SMBus Enable.This bit enables/disables the SMBus

Rev. 0.5 201C8051F340/1/2/3/4/5/6/717.4.2. SMB0CN Control RegisterSMB0CN is used to control the interface and to provide status information (see SFR D

C8051F340/1/2/3/4/5/6/7202 Rev. 0.5SFR Definition 17.2. SMB0CN: SMBus ControlBit7: MASTER: SMBus Master/Slave Indicator.This read-only bit indicates w

Rev. 0.5 203C8051F340/1/2/3/4/5/6/7Table 17.3. Sources for Hardware Changes to SMB0CNBit Set by Hardware When: Cleared by Hardware When:MASTER• A STAR

C8051F340/1/2/3/4/5/6/7204 Rev. 0.517.4.3. Data RegisterThe SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has

Rev. 0.5 205C8051F340/1/2/3/4/5/6/7Figure 17.5. Typical Master Transmitter SequenceA AAS W PData Byte Data ByteSLAS = STARTP = STOPA = ACKW = WRITESLA

C8051F340/1/2/3/4/5/6/7206 Rev. 0.517.5.2. Master Receiver ModeSerial data is received on SDA while the serial clock is output on SCL. The SMBus inter

Rev. 0.5 207C8051F340/1/2/3/4/5/6/717.5.3. Slave Receiver ModeSerial data is received on SDA and the clock is received on SCL. When slave events are e

C8051F340/1/2/3/4/5/6/7208 Rev. 0.517.5.4. Slave Transmitter ModeSerial data is transmitted on SDA and the clock is received on SCL. When slave events

Rev. 0.5 209C8051F340/1/2/3/4/5/6/7Table 17.4. SMBus Status Decoding ModeValues ReadCurrent SMbus State Typical Response OptionsValues WrittenStatus

Rev. 0.5 21C8051F340/1/2/3/4/5/6/71.1. CIP-51™ Microcontroller Core1.1.1. Fully 8051 CompatibleThe C8051F340/1/2/3/4/5/6/7 family utilizes Silicon Lab

C8051F340/1/2/3/4/5/6/7210 Rev. 0.5Slave Transmitter0100000A slave byte was transmitted; NACK received.No action required (expect-ing STOP condition).

Rev. 0.5 211C8051F340/1/2/3/4/5/6/718. UART0UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanc

C8051F340/1/2/3/4/5/6/7212 Rev. 0.518.1. Enhanced Baud Rate GenerationThe UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX cl

Rev. 0.5 213C8051F340/1/2/3/4/5/6/7Figure 18.3. UART Interconnect Diagram18.2.1. 8-Bit UART8-Bit UART mode uses a total of 10 bits per data byte: one

C8051F340/1/2/3/4/5/6/7214 Rev. 0.518.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first),

Rev. 0.5 215C8051F340/1/2/3/4/5/6/7Figure 18.6. UART Multi-Processor Mode Interconnect DiagramMasterDeviceSlaveDeviceTXRX RX TXSlaveDeviceRX TXSlaveDe

C8051F340/1/2/3/4/5/6/7216 Rev. 0.5SFR Definition 18.1. SCON0: Serial Port 0 ControlBit7: S0MODE: Serial Port 0 Operation Mode.This bit selects the UA

Rev. 0.5 217C8051F340/1/2/3/4/5/6/7SFR Definition 18.2. SBUF0: Serial (UART0) Port Data BufferBits7–0: SBUF0[7:0]: Serial Data Buffer Bits 7–0 (MSB-LS

C8051F340/1/2/3/4/5/6/7218 Rev. 0.5 Table 18.1. Timer Settings for Standard Baud Rates Using The Internal OscillatorTarget Baud Rate (bps)ActualBaud R

Rev. 0.5 219C8051F340/1/2/3/4/5/6/719. UART1 (C8051F340/1/4/5 Only)UART1 is an asynchronous, full duplex serial port offering a variety of data format

C8051F340/1/2/3/4/5/6/722 Rev. 0.5Figure 1.3. On-Chip Clock and ResetPCAWDTMissing Clock Detector (one-shot)Software Reset (SWRSF) System ResetReset F

C8051F340/1/2/3/4/5/6/7220 Rev. 0.519.1. Baud Rate GeneratorThe UART1 baud rate is generated by a dedicated 16-bit timer which runs from the controlle

Rev. 0.5 221C8051F340/1/2/3/4/5/6/719.2. Data FormatUART1 has a number of available options for data formatting. Data transfers begin with a start bit

C8051F340/1/2/3/4/5/6/7222 Rev. 0.519.3. Configuration and OperationUART1 provides standard asynchronous, full duplex communication. It can operate in

Rev. 0.5 223C8051F340/1/2/3/4/5/6/7byte in the FIFO. After SBUF1 is read, the next byte in the FIFO is loaded into SBUF1, and space is made available

C8051F340/1/2/3/4/5/6/7224 Rev. 0.5SFR Definition 19.1. SCON1: UART1 ControlBit7: OVR1: Receive FIFO Overrun Flag.This bit is used to indicate a recei

Rev. 0.5 225C8051F340/1/2/3/4/5/6/7SFR Definition 19.2. SMOD1: UART1 ModeBit7: MCE1: Multiprocessor Communication Enable.0: RI will be activated if st

C8051F340/1/2/3/4/5/6/7226 Rev. 0.5SFR Definition 19.3. SBUF1: UART1 Data BufferSFR Definition 19.4. SBCON1: UART1 Baud Rate Generator ControlBits7–0:

Rev. 0.5 227C8051F340/1/2/3/4/5/6/7SFR Definition 19.5. SBRLH1: UART1 Baud Rate Generator High ByteSFR Definition 19.6. SBRLL1: UART1 Baud Rate Genera

C8051F340/1/2/3/4/5/6/7228 Rev. 0.5NOTES:

Rev. 0.5 229C8051F340/1/2/3/4/5/6/720. Enhanced Serial Peripheral Interface (SPI0)The Enhanced Serial Peripheral Interface (SPI0) provides access to a

Rev. 0.5 23C8051F340/1/2/3/4/5/6/71.2. On-Chip MemoryThe CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of d

C8051F340/1/2/3/4/5/6/7230 Rev. 0.520.1. Signal DescriptionsThe four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 20.1.1. Master O

Rev. 0.5 231C8051F340/1/2/3/4/5/6/720.2. SPI0 Master Mode OperationA SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in ma

C8051F340/1/2/3/4/5/6/7232 Rev. 0.5Figure 20.2. Multiple-Master Mode Connection DiagramFigure 20.3. 3-Wire Single Master and Slave Mode Connection Dia

Rev. 0.5 233C8051F340/1/2/3/4/5/6/720.3. SPI0 Slave Mode OperationWhen SPI0 is enabled and not configured as a master, it will operate as a SPI slave.

C8051F340/1/2/3/4/5/6/7234 Rev. 0.520.5. Serial Clock TimingFour combinations of serial clock phase and polarity can be selected using the clock contr

Rev. 0.5 235C8051F340/1/2/3/4/5/6/7Figure 20.6. Slave Mode Data/Clock Timing (CKPHA = 0) Figure 20.7. Slave Mode Data/Clock Timing (CKPHA = 1)MSB Bit

C8051F340/1/2/3/4/5/6/7236 Rev. 0.520.6. SPI Special Function RegistersSPI0 is accessed and controlled through four special function registers in the

Rev. 0.5 237C8051F340/1/2/3/4/5/6/7SFR Definition 20.2. SPI0CN: SPI0 ControlBit 7: SPIF: SPI0 Interrupt Flag.This bit is set to logic 1 by hardware at

C8051F340/1/2/3/4/5/6/7238 Rev. 0.5SFR Definition 20.3. SPI0CKR: SPI0 Clock RateSFR Definition 20.4. SPI0DAT: SPI0 DataBits 7–0: SCR7–SCR0: SPI0 Clock

Rev. 0.5 239C8051F340/1/2/3/4/5/6/7Figure 20.8. SPI Master Timing (CKPHA = 0)Figure 20.9. SPI Master Timing (CKPHA = 1)SCK*TMCKHTMCKLMOSITMISMISO* SCK

C8051F340/1/2/3/4/5/6/724 Rev. 0.51.3. Universal Serial Bus ControllerThe Universal Serial Bus Controller (USB0) is a USB 2.0 compliant Full or Low Sp

C8051F340/1/2/3/4/5/6/7240 Rev. 0.5Figure 20.10. SPI Slave Timing (CKPHA = 0)Figure 20.11. SPI Slave Timing (CKPHA = 1)SCK*TSENSSTCKHTCKLMOSITSISTSIHM

Rev. 0.5 241C8051F340/1/2/3/4/5/6/7Table 20.1. SPI Slave Timing ParametersParameter Description Min Max UnitsMaster Mode Timing* (See Figure 20.8 and

C8051F340/1/2/3/4/5/6/7242 Rev. 0.5NOTES:

Rev. 0.5 243C8051F340/1/2/3/4/5/6/721. Timers Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the

C8051F340/1/2/3/4/5/6/7244 Rev. 0.5The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low trans

Rev. 0.5 245C8051F340/1/2/3/4/5/6/721.1.3. Mode 2: 8-bit Counter/Timer with Auto-ReloadMode 2 configures Timer 0 and Timer 1 to operate as 8-bit count

C8051F340/1/2/3/4/5/6/7246 Rev. 0.521.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)In Mode 3, Timer 0 is configured as two separate 8-bit count

Rev. 0.5 247C8051F340/1/2/3/4/5/6/7SFR Definition 21.1. TCON: Timer ControlBit7: TF1: Timer 1 Overflow Flag.Set by hardware when Timer 1 overflows. Th

C8051F340/1/2/3/4/5/6/7248 Rev. 0.5SFR Definition 21.2. TMOD: Timer ModeBit7: GATE1: Timer 1 Gate Control.0: Timer 1 enabled when TR1 = 1 irrespective

Rev. 0.5 249C8051F340/1/2/3/4/5/6/7SFR Definition 21.3. CKCON: Clock ControlBit7: T3MH: Timer 3 High Byte Clock Select.This bit selects the clock supp

Rev. 0.5 25C8051F340/1/2/3/4/5/6/71.4. Voltage RegulatorC8051F340/1/2/3/4/5/6/7 devices include a voltage regulator (REG0). When enabled, the REG0 out

C8051F340/1/2/3/4/5/6/7250 Rev. 0.5SFR Definition 21.4. TL0: Timer 0 Low ByteSFR Definition 21.5. TL1: Timer 1 Low ByteSFR Definition 21.6. TH0: Timer

Rev. 0.5 251C8051F340/1/2/3/4/5/6/721.2. Timer 2Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 ma

C8051F340/1/2/3/4/5/6/7252 Rev. 0.521.2.2. 8-bit Timers with Auto-ReloadWhen T2SPLIT = ‘1’ and T2CE = ‘0’, Timer 2 operates as two 8-bit timers (TMR2H

Rev. 0.5 253C8051F340/1/2/3/4/5/6/721.2.3. Timer 2 Capture Modes: USB Start-of-Frame or LFO Falling EdgeWhen T2CE = ‘1’, Timer 2 will operate in one o

C8051F340/1/2/3/4/5/6/7254 Rev. 0.5When T2SPLIT = ‘1’, the Timer 2 registers (TMR2H and TMR2L) act as two 8-bit counters. Each counter counts up indep

Rev. 0.5 255C8051F340/1/2/3/4/5/6/7SFR Definition 21.8. TMR2CN: Timer 2 ControlBit7: TF2H: Timer 2 High Byte Overflow Flag.Set by hardware when the Ti

C8051F340/1/2/3/4/5/6/7256 Rev. 0.5SFR Definition 21.9. TMR2RLL: Timer 2 Reload Register Low ByteSFR Definition 21.10. TMR2RLH: Timer 2 Reload Registe

Rev. 0.5 257C8051F340/1/2/3/4/5/6/721.3. Timer 3Timer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 ma

C8051F340/1/2/3/4/5/6/7258 Rev. 0.521.3.2. 8-bit Timers with Auto-ReloadWhen T3SPLIT is ‘1’ and T3CE = ‘0’, Timer 3 operates as two 8-bit timers (TMR3

Rev. 0.5 259C8051F340/1/2/3/4/5/6/721.3.3. USB Start-of-Frame CaptureWhen T3CE = ‘1’, Timer 3 will operate in one of two special capture modes. The ca

C8051F340/1/2/3/4/5/6/726 Rev. 0.51.6. Programmable Digital I/O and CrossbarC8051F340/1/4/5 devices include 40 I/O pins (five byte-wide Ports); C8051F

C8051F340/1/2/3/4/5/6/7260 Rev. 0.5When T3SPLIT = ‘1’, the Timer 3 registers (TMR3H and TMR3L) act as two 8-bit counters. Each counter counts up indep

Rev. 0.5 261C8051F340/1/2/3/4/5/6/7SFR Definition 21.13. TMR3CN: Timer 3 ControlBit7: TF3H: Timer 3 High Byte Overflow Flag.Set by hardware when the T

C8051F340/1/2/3/4/5/6/7262 Rev. 0.5SFR Definition 21.14. TMR3RLL: Timer 3 Reload Register Low ByteSFR Definition 21.15. TMR3RLH: Timer 3 Reload Regist

Rev. 0.5 263C8051F340/1/2/3/4/5/6/722. Programmable Counter Array (PCA0)The Programmable Counter Array (PCA0) provides enhanced timer functionality wh

C8051F340/1/2/3/4/5/6/7264 Rev. 0.522.1. PCA Counter/TimerThe 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high

Rev. 0.5 265C8051F340/1/2/3/4/5/6/722.2. Capture/Compare ModulesEach module can be configured to operate independently in one of six operation modes:

C8051F340/1/2/3/4/5/6/7266 Rev. 0.522.2.1. Edge-triggered Capture ModeIn this mode, a valid transition on the CEXn pin causes the PCA to capture the v

Rev. 0.5 267C8051F340/1/2/3/4/5/6/722.2.2. Software Timer (Compare) ModeIn Software Timer mode, the PCA counter/timer value is compared to the module&

C8051F340/1/2/3/4/5/6/7268 Rev. 0.522.2.3. High Speed Output ModeIn High Speed Output mode, a module’s associated CEXn pin is toggled each time a matc

Rev. 0.5 269C8051F340/1/2/3/4/5/6/722.2.4. Frequency Output ModeFrequency Output Mode produces a programmable-frequency square wave on the module’s as

Rev. 0.5 27C8051F340/1/2/3/4/5/6/71.7. Serial PortsThe C8051F340/1/2/3/4/5/6/7 Family includes an SMBus/I2C interface, full-duplex UARTs, and an Enhan

C8051F340/1/2/3/4/5/6/7270 Rev. 0.522.2.5. 8-Bit Pulse Width Modulator ModeEach module can be used independently to generate a pulse width modulated (

Rev. 0.5 271C8051F340/1/2/3/4/5/6/722.2.6. 16-Bit Pulse Width Modulator ModeA PCA module may also be operated in 16-Bit PWM mode. In this mode, the 16

C8051F340/1/2/3/4/5/6/7272 Rev. 0.522.3. Watchdog Timer ModeA programmable watchdog timer (WDT) function is available through the PCA Module 4. The WD

Rev. 0.5 273C8051F340/1/2/3/4/5/6/7Equation 22.4. Watchdog Timer Offset in PCA ClocksThe WDT reset is generated when PCA0L overflows while there is a

C8051F340/1/2/3/4/5/6/7274 Rev. 0.522.4. Register Descriptions for PCAFollowing are detailed descriptions of the special function registers related to

Rev. 0.5 275C8051F340/1/2/3/4/5/6/7SFR Definition 22.2. PCA0MD: PCA ModeBit7: CIDL: PCA Counter/Timer Idle Control. Specifies PCA behavior when CPU i

C8051F340/1/2/3/4/5/6/7276 Rev. 0.5SFR Definition 22.3. PCA0CPMn: PCA Capture/Compare ModePCA0CPMn Address: PCA0CPM0 = 0xDA (n = 0), PCA0CPM1 = 0xDB

Rev. 0.5 277C8051F340/1/2/3/4/5/6/7SFR Definition 22.4. PCA0L: PCA Counter/Timer Low ByteSFR Definition 22.5. PCA0H: PCA Counter/Timer High ByteSFR De

C8051F340/1/2/3/4/5/6/7278 Rev. 0.5SFR Definition 22.7. PCA0CPHn: PCA Capture Module High BytePCA0CPHn Address: PCA0CPH0 = 0xFC (n = 0), PCA0CPH1 = 0x

Rev. 0.5 279C8051F340/1/2/3/4/5/6/723. C2 InterfaceC8051F340/1/2/3/4/5/6/7 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allo

C8051F340/1/2/3/4/5/6/728 Rev. 0.51.9. 10-Bit Analog to Digital ConverterThe C8051F340/1/2/3/4/5/6/7 devices include an on-chip 10-bit SAR ADC with a

C8051F340/1/2/3/4/5/6/7280 Rev. 0.5C2 Register Definition 23.3. REVID: C2 Revision IDC2 Register Definition 23.4. FPCTL: C2 Flash Programming ControlC

Rev. 0.5 281C8051F340/1/2/3/4/5/6/723.2. C2 Pin SharingThe C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging

C8051F340/1/2/3/4/5/6/7282 Rev. 0.5CONTACT INFORMATIONSilicon Laboratories Inc.4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 41

Rev. 0.5 29C8051F340/1/2/3/4/5/6/71.10. ComparatorsC8051F340/1/2/3/4/5/6/7 devices include two on-chip voltage comparators that are enabled/disabled a

Rev. 0.5 3C8051F340/1/2/3/4/5/6/7Table Of Contents1. System Overview...

C8051F340/1/2/3/4/5/6/730 Rev. 0.52. Absolute Maximum RatingsTable 2.1. Absolute Maximum Ratings*Parameter Conditions Min Typ Max UnitsAmbient tempera

Rev. 0.5 31C8051F340/1/2/3/4/5/6/73. Global DC Electrical CharacteristicsOther electrical characteristics tables are found in the data sheet section c

C8051F340/1/2/3/4/5/6/732 Rev. 0.5Table 3.2. Index to Electrical Characteristics TablesTable TitlePage No.ADC0 Electrical Characteristics 56Voltage Re

Rev. 0.5 33C8051F340/1/2/3/4/5/6/74. Pinout and Package DefinitionsTable 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7 NamePin NumbersType Des

C8051F340/1/2/3/4/5/6/734 Rev. 0.5P1.0 46 26 D I/O orA InPort 1.0. See Section 15 for a complete description of Port 1.P1.1 45 25 D I/O orA InPort 1.1

Rev. 0.5 35C8051F340/1/2/3/4/5/6/7P3.3 27 - D I/O orA InPort 3.3.P3.4 26 - D I/O orA InPort 3.4.P3.5 25 - D I/O orA InPort 3.5.P3.6 24 - D I/O orA InP

C8051F340/1/2/3/4/5/6/736 Rev. 0.5Figure 4.1. TQFP-48 Pinout Diagram (Top View)123456789101112363534333231302928272625484746454443424140393837VBUSP2.2

Rev. 0.5 37C8051F340/1/2/3/4/5/6/7Figure 4.2. TQFP-48 Package DiagramEE1DD1481A1ebPIN 1 IDENTIFIERA2ATable 4.2. TQFP-48 Package DimensionsMMMIN TYP MA

C8051F340/1/2/3/4/5/6/738 Rev. 0.5Figure 4.3. LQFP-32 Pinout Diagram (Top View)1VBUSP1.2P1.7P1.4P1.3P1.5D+D-GNDP0.1P0.0P2.0P2.123456782423222120191817

Rev. 0.5 39C8051F340/1/2/3/4/5/6/7Figure 4.4. LQFP-32 Package DiagramPIN 1IDENTIFIERA1eb132E1D1DEA2ATable 4.3. LQFP-32 Package DimensionsMMMIN TYP MAX

C8051F340/1/2/3/4/5/6/74 Rev. 0.59.3. Interrupt Handler...

C8051F340/1/2/3/4/5/6/740 Rev. 0.5NOTES:

Rev. 0.5 41C8051F340/1/2/3/4/5/6/75. 10-Bit ADC (ADC0)The ADC0 subsystem for the C8051F340/1/2/3/4/5/6/7 consists of two analog multiplexers (referred

C8051F340/1/2/3/4/5/6/742 Rev. 0.55.1. Analog MultiplexerAMUX0 selects the positive and negative inputs to the ADC. The positive input (AIN+) can be c

Rev. 0.5 43C8051F340/1/2/3/4/5/6/75.2. Temperature SensorThe temperature sensor transfer function is shown in Figure 5.2. The output voltage (VTEMP) i

C8051F340/1/2/3/4/5/6/744 Rev. 0.5Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V)-40.00 -20.000.0020.0040.0060.0080.00Te

Rev. 0.5 45C8051F340/1/2/3/4/5/6/75.3. Modes of OperationADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided versi

C8051F340/1/2/3/4/5/6/746 Rev. 0.55.3.2. Tracking ModesThe AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, t

Rev. 0.5 47C8051F340/1/2/3/4/5/6/75.3.3. Settling Time RequirementsWhen the ADC0 input configuration is changed (i.e., a different AMUX0 selection is

C8051F340/1/2/3/4/5/6/748 Rev. 0.5SFR Definition 5.1. AMX0P: AMUX0 Positive Channel SelectBits7–5: UNUSED. Read = 000b; Write = don’t care.Bits4–0: AM

Rev. 0.5 49C8051F340/1/2/3/4/5/6/7SFR Definition 5.2. AMX0N: AMUX0 Negative Channel SelectBits7–5: UNUSED. Read = 000b; Write = don’t care.Bits4–0: AM

Rev. 0.5 5C8051F340/1/2/3/4/5/6/714.Oscillators...

C8051F340/1/2/3/4/5/6/750 Rev. 0.5SFR Definition 5.3. ADC0CF: ADC0 ConfigurationSFR Definition 5.4. ADC0H: ADC0 Data Word MSBSFR Definition 5.5. ADC0L

Rev. 0.5 51C8051F340/1/2/3/4/5/6/7SFR Definition 5.6. ADC0CN: ADC0 ControlBit7: AD0EN: ADC0 Enable Bit.0: ADC0 Disabled. ADC0 is in low-power shutdown

C8051F340/1/2/3/4/5/6/752 Rev. 0.55.4. Programmable Window DetectorThe ADC Programmable Window Detector continuously compares the ADC0 conversion resu

Rev. 0.5 53C8051F340/1/2/3/4/5/6/7SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High ByteSFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte

C8051F340/1/2/3/4/5/6/754 Rev. 0.55.4.1. Window Detector In Single-Ended ModeFigure 5.6 shows two example window comparisons for right-justified, sing

Rev. 0.5 55C8051F340/1/2/3/4/5/6/75.4.2. Window Detector In Differential ModeFigure 5.8 shows two example window comparisons for right-justified, diff

C8051F340/1/2/3/4/5/6/756 Rev. 0.5Table 5.1. ADC0 Electrical CharacteristicsVDD = 3.0 V, VREF = 2.40 V, –40 to +85 °C unless otherwise specifiedParame

Rev. 0.5 57C8051F340/1/2/3/4/5/6/76. Voltage ReferenceThe Voltage reference MUX on C8051F340/1/2/3/4/5/6/7 devices is configurable to use an externall

C8051F340/1/2/3/4/5/6/758 Rev. 0.5SFR Definition 6.1. REF0CN: Reference ControlTable 6.1. Voltage Reference Electrical CharacteristicsVDD = 3.0 V; –40

Rev. 0.5 59C8051F340/1/2/3/4/5/6/77. ComparatorsC8051F340/1/2/3/4/5/6/7 devices include two on-chip programmable voltage Comparators. A block dia-gram

C8051F340/1/2/3/4/5/6/76 Rev. 0.517.3.SMBus Operation ... 1941

C8051F340/1/2/3/4/5/6/760 Rev. 0.5Figure 7.1. Comparator Functional Block DiagramComparator outputs can be polled in software, used as an interrupt so

Rev. 0.5 61C8051F340/1/2/3/4/5/6/7 Figure 7.2. Comparator Hysteresis PlotComparator hysteresis is programmed using Bits3-0 in the Comparator Control R

C8051F340/1/2/3/4/5/6/762 Rev. 0.5SFR Definition 7.1. CPT0CN: Comparator0 ControlBit7: CP0EN: Comparator0 Enable Bit.0: Comparator0 Disabled.1: Compar

Rev. 0.5 63C8051F340/1/2/3/4/5/6/7SFR Definition 7.2. CPT0MX: Comparator0 MUX SelectionBit7: UNUSED. Read = 0b, Write = don’t care.Bits6–4: CMX0N2–CMX

C8051F340/1/2/3/4/5/6/764 Rev. 0.5SFR Definition 7.3. CPT0MD: Comparator0 Mode SelectionBits7–6: UNUSED. Read = 00b. Write = don’t care.Bit5: CP0RIE:

Rev. 0.5 65C8051F340/1/2/3/4/5/6/7SFR Definition 7.4. CPT1CN: Comparator1 ControlBit7: CP1EN: Comparator1 Enable Bit.0: Comparator1 Disabled.1: Compar

C8051F340/1/2/3/4/5/6/766 Rev. 0.5SFR Definition 7.5. CPT1MX: Comparator1 MUX SelectionBit7: UNUSED. Read = 0b, Write = don’t care.Bits6–4: CMX1N2–CMX

Rev. 0.5 67C8051F340/1/2/3/4/5/6/7SFR Definition 7.6. CPT1MD: Comparator1 Mode SelectionBits7–6: UNUSED. Read = 00b, Write = don’t care.Bit5: CP1RIE:

C8051F340/1/2/3/4/5/6/768 Rev. 0.5 Table 7.1. Comparator Electrical CharacteristicsVDD = 3.0 V, –40 to +85 °C unless otherwise noted. All specificatio

Rev. 0.5 69C8051F340/1/2/3/4/5/6/78. Voltage Regulator (REG0)C8051F340/1/2/3/4/5/6/7 devices include a voltage regulator (REG0). When enabled, the REG

Rev. 0.5 7C8051F340/1/2/3/4/5/6/721.2.Timer 2 ...

C8051F340/1/2/3/4/5/6/770 Rev. 0.5Figure 8.1. REG0 Configuration: USB Bus-PoweredFigure 8.2. REG0 Configuration: USB Self-PoweredVoltage Regulator (RE

Rev. 0.5 71C8051F340/1/2/3/4/5/6/7Figure 8.3. REG0 Configuration: USB Self-Powered, Regulator DisabledFigure 8.4. REG0 Configuration: No USB Connectio

C8051F340/1/2/3/4/5/6/772 Rev. 0.5SFR Definition 8.1. REG0CN: Voltage Regulator ControlBit7: REGDIS: Voltage Regulator Disable.0: Voltage Regulator En

Rev. 0.5 73C8051F340/1/2/3/4/5/6/79. CIP-51 MicrocontrollerThe MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatibl

C8051F340/1/2/3/4/5/6/774 Rev. 0.5PerformanceThe CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the st

Rev. 0.5 75C8051F340/1/2/3/4/5/6/7CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock cycles for each in

C8051F340/1/2/3/4/5/6/776 Rev. 0.5ORL A, direct OR direct byte to A 2 2ORL A, @Ri OR indirect RAM to A 1 2ORL A, #data OR immediate to A 2 2ORL direct

Rev. 0.5 77C8051F340/1/2/3/4/5/6/7XCH A, @Ri Exchange indirect RAM with A 1 2XCHD A, @Ri Exchange low nibble of indirect RAM with A 1 2Boolean Manipul

C8051F340/1/2/3/4/5/6/778 Rev. 0.5Notes on Registers, Operands and Addressing Modes:Rn - Register R0-R7 of the currently selected register bank.@Ri -

Rev. 0.5 79C8051F340/1/2/3/4/5/6/79.2. Memory OrganizationThe memory organization of the CIP-51 System Controller is similar to that of a standard 805

C8051F340/1/2/3/4/5/6/78 Rev. 0.5NOTES:

C8051F340/1/2/3/4/5/6/780 Rev. 0.59.2.2. Data MemoryThe CIP-51 includes 256 of internal RAM mapped into the data memory space from 0x00 through 0xFF.

Rev. 0.5 81C8051F340/1/2/3/4/5/6/79.2.6. Special Function RegistersThe direct-access data memory locations from 0x80 to 0xFF constitute the special fu

C8051F340/1/2/3/4/5/6/782 Rev. 0.5Table 9.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserv

Rev. 0.5 83C8051F340/1/2/3/4/5/6/7P1MDIN 0xF2 Port 1 Input Mode Configuration 156P1MDOUT 0xA5 Port 1 Output Mode Configuration 156P1SKIP 0xD5 Port 1 S

C8051F340/1/2/3/4/5/6/784 Rev. 0.5SBUF0 0x99 UART0 Data Buffer 217SCON0 0x98 UART0 Control 216SMB0CF 0xC1 SMBus Configuration 200SMB0CN 0xC0 SMBus Con

Rev. 0.5 85C8051F340/1/2/3/4/5/6/79.2.7. Register DescriptionsFollowing are descriptions of SFRs related to the operation of the CIP-51 System Control

C8051F340/1/2/3/4/5/6/786 Rev. 0.5SFR Definition 9.4. PSW: Program Status WordSFR Definition 9.5. ACC: AccumulatorBit7: CY: Carry Flag.This bit is set

Rev. 0.5 87C8051F340/1/2/3/4/5/6/7SFR Definition 9.6. B: B Register9.3. Interrupt HandlerThe CIP-51 includes an extended interrupt system supporting m

C8051F340/1/2/3/4/5/6/788 Rev. 0.5/INT0 and /INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 9.13). Note that /IN

Rev. 0.5 89C8051F340/1/2/3/4/5/6/79.3.5. Interrupt Register DescriptionsThe SFRs used to enable the interrupt sources and set their priority level are

Rev. 0.5 9C8051F340/1/2/3/4/5/6/7List of Figures and Tables1. System OverviewTable 1.1. Product Selection Guide ...

C8051F340/1/2/3/4/5/6/790 Rev. 0.5SFR Definition 9.7. IE: Interrupt EnableBit7: EA: Enable All Interrupts.This bit globally enables/disables all inter

Rev. 0.5 91C8051F340/1/2/3/4/5/6/7SFR Definition 9.8. IP: Interrupt PriorityBit7: UNUSED. Read = 1, Write = don't care.Bit6: PSPI0: Serial Periph

C8051F340/1/2/3/4/5/6/792 Rev. 0.5SFR Definition 9.9. EIE1: Extended Interrupt Enable 1Bit7: ET3: Enable Timer 3 Interrupt.This bit sets the masking o

Rev. 0.5 93C8051F340/1/2/3/4/5/6/7SFR Definition 9.10. EIP1: Extended Interrupt Priority 1Bit7: PT3: Timer 3 Interrupt Priority Control. This bit sets

C8051F340/1/2/3/4/5/6/794 Rev. 0.5SFR Definition 9.11. EIE2: Extended Interrupt Enable 2SFR Definition 9.12. EIP2: Extended Interrupt Priority 2Bits7–

Rev. 0.5 95C8051F340/1/2/3/4/5/6/7SFR Definition 9.13. IT01CF: INT0/INT1 ConfigurationBit7: IN1PL: /INT1 Polarity0: /INT1 input is active low.1: /INT1

C8051F340/1/2/3/4/5/6/796 Rev. 0.59.4. Power Management ModesThe CIP-51 core has two software programmable power management modes: Idle and Stop. Idle

Rev. 0.5 97C8051F340/1/2/3/4/5/6/7SFR Definition 9.14. PCON: Power ControlBits7–2: GF5–GF0: General Purpose Flags 5–0. These are general purpose flags

C8051F340/1/2/3/4/5/6/798 Rev. 0.5NOTES:

Rev. 0.5 99C8051F340/1/2/3/4/5/6/710. Prefetch EngineThe C8051F340/1/2/3/4/5/6/7 family of devices incorporate a 2-byte prefetch engine. Because the a