Silicon Laboratories SI5365 Manuel d'utilisateur

Rev. 1.0 9/14 Copyright © 2014 by Silicon Laboratories Si5365Si5365PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIERFeaturesApplicationsDescriptionThe Si536

Si536510 Rev. 1.0Table 3. Jitter GenerationParameter SymbolTest Condition*Min Typ Max UnitMeasurement Filter DSPLL BW2Jitter Gen OC-192JGEN 4–80 MHz 1

Si5365Rev. 1.0 11Figure 3. Typical Phase Noise PlotTable 5. Absolute Maximum LimitsParameterSymbol Value UnitDC Supply Voltage VDD–0.5 to 3.8 VLVCMOS

Si536512 Rev. 1.02. Typical Application SchematicFigure 4. Si5365 Typical Application CircuitSi5365CKIN1+CKIN1–CKSEL[1:0]3ALRMOUTCnBRSTCKOUT1+CKOUT1–

Si5365Rev. 1.0 133. Functional DescriptionThe Si5365 is a low jitter, precision clock multiplier forhigh-speed communication systems, including SONET

Si536514 Rev. 1.04. Pin Descriptions: Si53651234567891011121314151648474645444342414039383736353433313029282726 3264616263575859605051525354555649AUT

Si5365Rev. 1.0 15Table 6. Si5365 Pin Descriptions Pin # Pin Name I/O Signal Level Description1, 2, 17, 20, 23, 24, 25, 47, 48, 49, 52, 53, 72, 73, 74,

Si536516 Rev. 1.09C1BOLVCMOSCKIN1 Invalid Indicator.This pin is an active high alarm output associated with CKIN1. Once triggered, the alarm will rema

Si5365Rev. 1.0 173435CKIN2+CKIN2–IMULTIClock Input 2.Differential input clock. This input can also be driven with a single-ended signal.37 DBL2_BY I 3

Si536518 Rev. 1.06061BWSEL0BWSEL1I 3-Level Bandwidth Select.These pins are three level inputs that select the DSPLL closed loop bandwidth according to

Si5365Rev. 1.0 198095SFOUT1SFOUT0I 3-Level Signal Format Select.Three level inputs that select the output signal format (common mode voltage and diffe

Si53652 Rev. 1.0Functional Block DiagramManual/Auto SwitchCKOUT2CKIN1CKOUT1CKIN2Control÷ NC1÷ NC2Clock SelectCKIN3CKIN4CKOUT4÷ NC4CKOUT5÷ NC5VDD (1.8,

Si536520 Rev. 1.09798CKOUT4–CKOUT4+OMULTIClock Output 4.Differential output clock with a frequency specified by FRQSEL and FRQTBL settings. Output sig

Si5365Rev. 1.0 215. Ordering GuideOrdering Part Number Package ROHS6, Pb-Free Temperature RangeSi5365-C-GQ* 100-Pin 14 x 14 mm TQFP Yes –40 to 85 °C*

Si536522 Rev. 1.06. Package Outline: 100-Pin TQFPFigure 5 illustrates the package details for the Si5365. Table 7 lists the values for the dimensions

Si5365Rev. 1.0 237. PCB Land PatternFigure 6. PCB Land Pattern Diagram

Si536524 Rev. 1.0Table 8. PCB Land Pattern DimensionsDimension MIN MAXe0.50 BSC.E 15.40 REF.D 15.40 REF.E2 3.90 4.10D2 3.90 4.10GE 13.90 —GD 13.90 —X

Si5365Rev. 1.0 258. Top Marking8.1. Si5365 Top Marking8.2. Top Marking ExplanationMark Method: LaserLogo Size: 9.2 x 3.1 mmCenter-JustifiedFont Siz

Si536526 Rev. 1.0DOCUMENT CHANGE LISTRevision 0.32 to Revision 0.33 Condensed format.Revision 0.33 to Revision 0.34 Removed references to latency co

Si5365Rev. 1.0 27NOTES:

Si536528 Rev. 1.0CONTACT INFORMATIONSilicon Laboratories Inc.400 West Cesar ChavezAustin, TX 78701Tel: 1+(512) 416-8500Fax: 1+(512) 416-9669Toll Free:

Si5365Rev. 1.0 3TABLE OF CONTENTSSection Page1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Si53654 Rev. 1.01. Electrical SpecificationsTable 1. DC Characteristics(VDD= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)Parameter Symbol Te

Si5365Rev. 1.0 5Output Clocks (CKOUTn)3Common Mode CKOVCMLVPECL 100  load line-to-lineVDD –1.42—VDD –1.25 VDifferential Output SwingCKOVDLVPECL 100 

Si53656 Rev. 1.02-Level LVCMOS Input PinsInput Voltage Low VILVDD=1.71V — — 0.5 VVDD=2.25V — — 0.7 VVDD=2.97V — — 0.8 VInput Voltage High VIHVDD=1.89V

Si5365Rev. 1.0 7Figure 1. Differential Voltage CharacteristicsFigure 2. Rise/Fall Time CharacteristicsLVCMOS Output PinsOutput Voltage Low VOLIO = 2 m

Si53658 Rev. 1.0Table 2. AC Specifications(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)Parameter Symbol Test Condition Min Typ Max Unit

Si5365Rev. 1.0 9LVCMOS Input PinsMinimum Reset Pulse WidthtRSTMN1µsInput Capacitance Cin—— 3 pFLVCMOS Output PinsRise/Fall Times tRFCLOAD= 20pfSee Fig