Silicon Laboratories SI5366 Manuel d'utilisateur

Rev. 1.0 8/12 Copyright © 2012 by Silicon Laboratories Si5366Si5366PRECISION CLOCK MULTIPLIER/JITTER ATTENUATORFeaturesApplicationsDescriptionThe Si53

Si536610 Rev. 1.0Output Rise/Fall (20–80%) @ 212.5 MHz outputCKOTRFCMOS OutputVDD=2.97CLOAD=5 pF—— 2 nsOutput Duty Cycle Uncertainty @ 622.08 MHzCKODC

Si5366Rev. 1.0 11PLL Performance(fin = fout = 622.08 MHz; BW = 120 Hz; LVPECL)Lock Time tLOCKMPStart of ICAL to of LOL — 35 1200 msOutput Clock Phas

Si536612 Rev. 1.0Table 4. Jitter GenerationParameter SymbolTest Condition*Min Typ Max GR-253-SpecificationUnitMeasurement FilterDSPLL BW2Jitter Gen OC

Si5366Rev. 1.0 13-Table 6. Absolute Maximum Ratings*Parameter Symbol Test Condition Min Typ Max UnitDC Supply Voltage VDD–0.5 — 3.8 VLVCMOS Input Volt

Si536614 Rev. 1.01. Typical Phase Noise PerformanceFigure 3. Typical Phase Noise PlotTable 7. RMS Jitter by BandJitter Band RMS JitterSONET_OC48, 12

Si5366Rev. 1.0 152. Typical Application SchematicFigure 4. Si5366 Typical Application CircuitSi5366CKIN1+CKIN1–CKSEL[1:0]3ALRMOUTCKnBLOLRATE2RSTCKOUT

Si536616 Rev. 1.03. Functional DescriptionThe Si5366 is a jitter-attenuating precision clockmultiplier for high-speed communication systems,including

Si5366Rev. 1.0 174. Pin Descriptions: Si5366 (Top View)1234567891011121314151648474645444342414039383736353433313029282726 32646162635758596050515253

Si536618 Rev. 1.0Table 8. Si5366 Pin Descriptions Pin # Pin Name I/O Signal Level Description1, 2, 23, 24, 25, 47, 48, 52, 53, 72, 73, 74, 75, 90NC No

Si5366Rev. 1.0 1910 C2B O LVCMOS CKIN2 Invalid Indicator.This pin is an active high alarm output associated with CKIN2. Once triggered, the alarm will

Si53662 Rev. 1.0Functional Block DiagramSkew ControlManual/Auto SwitchXtal or RefclockCKIN1 CKIN2 ControlClock SelectCKIN3 CKIN4 DSPLL®Resonator/Rate

Si536620 Rev. 1.021 FS_ALIGN I LVCMOS FSYNC Alignment Control.If CK_CONF = 1, a logic high on this pin causes the FS_OUT phase to be realigned to the

Si5366Rev. 1.0 2149 LOL O LVCMOS PLL Loss of Lock Indicator.This pin functions as the active high PLL loss of lock indicator.0 = PLL locked.1 = PLL un

Si536622 Rev. 1.056 FOS_CTL I 3-Level Frequency Offset Control.This pin enables or disables use of the CKIN2 FOS reference as an input to the clock se

Si5366Rev. 1.0 238095SFOUT1SFOUT0I 3-Level Signal Format Select.Three level inputs that select the output signal format (common mode voltage and diffe

Si536624 Rev. 1.09798CKOUT4–CKOUT4+OMULTIClock Output 4.Differential output clock with a frequency specified by FRQSEL and FRQTBL settings. Output sig

Si5366Rev. 1.0 255. Ordering GuideOrdering Part Number Package ROHS6, Pb-Free Temperature RangeSi5366-C-GQ 100-Pin 14 x 14 mm TQFP Yes –40 to 85 °C

Si536626 Rev. 1.06. Package Outline: 100-Pin TQFPFigure 5 illustrates the package details for the Si5366. Table 9 lists the values for the dimensions

Si5366Rev. 1.0 277. PCB Land PatternFigure 6. PCB Land Pattern Diagram

Si536628 Rev. 1.0Table 10. PCB Land Pattern DimensionsDimension MIN MAXe0.50 BSC.E 15.40 REF.D 15.40 REF.E2 3.90 4.10D2 3.90 4.10GE 13.90 —GD 13.90 —X

Si5366Rev. 1.0 298. Top Marking8.1. Si5366 Top Marking (TQFP)8.2. Top Marking ExplanationMark Method: LaserLogo Size: 9.2 x 3.1 mmCenter-JustifiedF

Si5366Rev. 1.0 3TABLE OF CONTENTSSection Page1. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Si536630 Rev. 1.0DOCUMENT CHANGE LISTRevision 0.1 to Revision 0.2 Updated Table 1, “Performance Specifications,” on page 4. Changed LVTTL to LVCMOS

Si5366Rev. 1.0 31NOTES:

Si536632 Rev. 1.0CONTACT INFORMATIONSilicon Laboratories Inc.400 West Cesar ChavezAustin, TX 78701Tel: 1+(512) 416-8500Fax: 1+(512) 416-9669Toll Free:

Si53664 Rev. 1.0Figure 1. Differential Voltage CharacteristicsFigure 2. Rise/Fall Time CharacteristicsTable 1. Recommended Operating Conditions1Parame

Si5366Rev. 1.0 5Table 2. DC Characteristics(VDD= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)Parameter Symbol Test Condition Min Typ Max UnitS

Si53666 Rev. 1.0Output Clocks (CKOUTn)3,5,6Common Mode CKOVCMLVPECL 100  load line-to-lineVDD –1.42 — VDD –1.25 VDifferential Output SwingCKOVDLVPECL

Si5366Rev. 1.0 72-Level LVCMOS Input PinsInput Voltage Low VILVDD=1.71V — — 0.5 VVDD=2.25V — — 0.7 VVDD=2.97V — — 0.8 VInput Voltage High VIHVDD=1.89V

Si53668 Rev. 1.03-Level Input Pins4Input Voltage Low VILL— — 0.15 x VDDVInput Voltage Mid VIMM0.45 x VDD—0.55xVDDVInput Voltage High VIHH0.85 x VDD——V

Si5366Rev. 1.0 9Table 3. AC Characteristics(VDD= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)Parameter Symbol Test Condition Min Typ Max UnitS