Silicon Laboratories SI5319 Manuel d'utilisateur télécharger pdf

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Si5319

PRELIMINARY DATA SHEET

ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Description

The Si5319 is a jitter-attenuating precision M/N clock

multiplier for applications requiring sub 1 ps jitter

performance. The Si5319 accepts one clock input ranging

from 2 kHz to 710 MHz and generates one clock output

ranging from 2 kHz to 945 MHz and select frequencies to

1.4 GHz. The Si5319 can also use its crystal oscillator as a

clock source for frequency synthesis. The device provides

virtually any frequency translation combination across this

operating range. The Si5319 input clock frequency and clock

multiplication ratio are programmable through an I

C or SPI

interface. The Si5319 is based on Silicon Laboratories' 3rd-

generation DSPLL

technology, which provides any-rate

frequency synthesis and jitter attenuation in a highly

integrated PLL solution that eliminates the need for external

VCXO and loop filter components. The DSPLL loop

bandwidth is digitally programmable, providing jitter

performance optimization at the application level. Operating

from a single 1.8, 2.5, or 3.3 V supply, the Si5319 is ideal for

providing clock multiplication and jitter attenuation in high

performance timing applications.

Applications

 SONET/SDH OC-48/STM-16 and OC-192/STM-64

line cards

 GbE/10GbE, 1/2/4/8/10GFC line cards

 ITU G.709 and custom FEC line cards

 Optical modules

 Wireless basestations

 Data converter clocking

 xDSL

 Synchronous Ethernet

 Test and measurement

 Discrete PLL replacement

 Broadcast video

Features

 Generates any frequency from 2 kHz to 945 MHz

and select frequencies to 1.4 GHz from an input

frequency of 2 kHz to 710 MHz

 Ultra-low jitter clock outputs with jitter generation as

low as 0.3ps rms (50kHz–80MHz)

 Integrated loop filter with selectable loop bandwidth

(60Hz to 8.4kHz)

 Meets OC-192 GR-253-CORE jitter specifications

 Clock or crystal input with manual clock selection

 Clock output selectable signal format

(LVPECL, LVDS, CML, CMOS)

 Support for ITU G.709 and custom FEC ratios

(255/238, 255/237, 255/236)

 Supports various frequency translations for

Synchronous Ethernet

 LOL, LOS alarm outputs

 I

C or SPI programmable

 On-chip voltage regulator for 1.8 V ±5%, 2.5 or

3.3 V ±10% operation

 Small size: 6 x 6 mm 36-lead QFN

 Pb-free, ROHS compliant

DSPLL

Loss of Signal

Xtal or Refclock

CKIN

CKOUT

÷ N31

÷ N2

Signal Detect

Device Interrupt

VDD (1.8, 2.5, or 3.3 V)

GND

Loss of Lock

Xtal/Clock Select

C/SPI Port

Control

Rate Select

÷ N32

÷ NC1_LS

N1_HS

1 2 3 4 5 6 ... 15 16

Résumé du contenu

Page 1 - PRELIMINARY DATA SHEET

Page 2

Si531910 Preliminary Rev. 0.33. Ordering GuideOrdering Part NumberOutput Clock Frequency RangePackageROHS6, Pb-FreeTemperature RangeSi5319A-C-GM 2 kH

Page 3 - (Continued)

Si5319Preliminary Rev. 0.3 114. Package Outline: 36-Pin QFNFigure 4 illustrates the package details for the Si5319. Table 3 lists the values for the

Page 4 - 155.52 MHz in, 622.08 MHz out

Si531912 Preliminary Rev. 0.35. Recommended PCB LayoutFigure 5. PCB Land Pattern Diagram

Page 5 - C Control Mode)

Si5319Preliminary Rev. 0.3 13Table 4. PCB Land Pattern DimensionsDimension MIN MAXe 0.50 BSC.E5.42 REF.D5.42 REF.E2 4.00 4.20D2 4.00 4.20GE 4.53 —GD 4

Page 6 - 1. Functional Description

Si531914 Preliminary Rev. 0.3DOCUMENT CHANGE LISTRevision 0.1 to Revision 0.2 Changed 1.8 V operating range to ±5%. Updated Table 1 on page 2. Upda

Page 7 - 2. Pin Descriptions: Si5319

Si5319Preliminary Rev. 0.3 15NOTES:

Page 8 - 8 Preliminary Rev. 0.3

Si531916 Preliminary Rev. 0.3CONTACT INFORMATIONSilicon Laboratories Inc.400 West Cesar ChavezAustin, TX 78701Tel: 1+(512) 416-8500Fax: 1+(512) 416-96

Page 9 - Preliminary Rev. 0.3 9

Si53192 Preliminary Rev. 0.3Table 1. Performance Specifications1(VDD= 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 ºC)Parameter Symbol Test Conditi

Page 10 - 3. Ordering Guide

Si5319Preliminary Rev. 0.3 3PLL PerformanceJitter Generation JGENfIN = fOUT = 622.08 MHz,LVPECL output format50 kHz–80 MHz— 0.3 TBD ps rms12 kHz–20 MH

Page 11 - Table 3. Package Dimensions

Si53194 Preliminary Rev. 0.3Figure 1. Typical Phase Noise PlotJitter Band Jitter, RMSBrick Wall, 100 Hz to 100 MHz 1,279 fsSONET_OC48, 12 kHz to 20 MH

Page 12 - 5. Recommended PCB Layout

Si5319Preliminary Rev. 0.3 5Figure 2. Si5319 Typical Application Circuit (I2C Control Mode)Figure 3. Si5319 Typical Application Circuit (SPI Control M

Page 13

Si53196 Preliminary Rev. 0.31. Functional DescriptionThe Si5319 is a jitter-attenuating precision clockmultiplier for applications requiring sub 1 ps

Page 14 - DOCUMENT CHANGE LIST

Si5319Preliminary Rev. 0.3 72. Pin Descriptions: Si5319Pin numbers are preliminary and subject to change.Pin # Pin Name I/O Signal Level Description1

Page 15 - Preliminary Rev. 0.3 15

Si53198 Preliminary Rev. 0.35, 10, 32VDDVDDSupplySupply.The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capaci-tors should be associated

Page 16 - CONTACT INFORMATION

Si5319Preliminary Rev. 0.3 923 SDA_SDO I/O LVCMOSSerial Data.In I2C control mode (CMODE = 0), this pin functions as the bidirec-tional serial data por