Silicon Laboratories SI5367 Manuel d'utilisateur télécharger pdf

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Si5368

ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Description

The Si5368 is a jitter-attenuating precision clock multiplier for

applications requiring sub 1 ps rms jitter performance. The

Si5368 accepts four clock inputs ranging from 2 kHz to

710 MHz and generates five clock outputs ranging from

2 kHz to 945 MHz and select frequencies to 1.4 GHz. The

device provides virtually any frequency translation

combination across this operating range. The outputs are

divided down separately from a common source. The Si5368

input clock frequency and clock multiplication ratio are

programmable through an I

C or SPI interface. The Si5368 is

based on Silicon Laboratories' third-generation DSPLL

technology, which provides any-rate frequency synthesis and

jitter attenuation in a highly integrated PLL solution that

eliminates the need for external VCXO and loop filter

components. The DSPLL loop bandwidth is digitally

programmable, providing jitter performance optimization at

the application level. Operating from a single 1.8, 2.5 ,or

3.3 V supply, the Si5368 is ideal for providing clock

multiplication and jitter attenuation in high performance timing

applications.

Applications

 SONET/SDH OC-48/STM-16/OC-192/STM-64 line cards

 GbE/10GbE, 1/2/4/8/10G FC line cards

 ITU G.709 and custom FEC line cards

 Wireless basestations

 Data converter clocking

 OTN/WDM Muxponder, MSPP, ROADM line cards

 SONET/SDH + PDH clock synthesis

 Test and measurement

 Synchronous Ethernet

 Broadcast video

Features

 Generates any frequency from 2 kHz to 945 MHz

and select frequencies to 1.4 GHz from an input

frequency of 2 kHz to 710 MHz

 Ultra-low jitter clock outputs with jitter generation as

low as 300 fs rms (50 kHz–80 MHz)

 Integrated loop filter with selectable loop bandwidth

(60Hz to 8.4kHz)

 Meets OC-192 GR-253-CORE jitter specifications

 Four clock inputs with manual or automatically

controlled hitless switching and phase build-out

 Supports holdover and freerun modes of operation

 Five clock outputs with selectable signal format

(LVPECL, LVDS, CML, CMOS)

 SONET frame sync switching and regeneration

 Support for ITU G.709 and custom FEC ratios

(253/226, 239/237, 255/238, 255/237, 255/236)

 LOL, LOS, FOS alarm outputs

 Digitally-controlled output phase adjust

 I

C or SPI programmable settings

 On-chip voltage regulator for 1.8 V ±5%, 2.5 V

±10%, or 3.3 V ±10% operation

 Small size: 14 x 14 mm 100-pin TQFP

 Pb-free, RoHS compliant

PRELIMINARY DATA SHEET

Rate Select

C/SPI Port

Clock Select

Xtal or Refclock

CKOUT2

CKIN1

CKOUT1

CKIN2

Control

Skew Control

CKIN3/FSYNC1

CKIN4

CKOUT4

CKOUT5/FS_OUT

Input Clock 3

Input Clock 4

Output Clock 2

VDD (1.8, 2.5, or 3.3 V)

GND

÷ N32

÷ N31

DSPLL

÷ N2

CKOUT3

÷ N33

÷ N34

Device Interrupt

LOL/LOS/FOS Alarms

FSYNC Realignment

÷ N1_HS

÷ NC1_LS

÷ NC2_LS

÷ NC3_LS

÷ NC4_LS

÷ NC5_LS

1 2 3 4 5 6 ... 77 78

Résumé du contenu

Page 1 - PRELIMINARY DATA SHEET

Page 2 - 2 Preliminary Rev. 0.41

Si536810 Preliminary Rev. 0.412. Pin Descriptions: Si5368Table 3. Si5368 Pin Descriptions Pin # Pin Name I/O Signal Level Description1, 2, 4, 20, 22,

Page 3 - TABLE OF CONTENTS

Si5368Preliminary Rev. 0.41 115, 6, 15, 27, 62, 63, 76, 79, 81, 84, 86, 89, 91, 94, 96, 99, 100VDDVdd Supply VDD.The device operates from a 1.8, 2.5,

Page 4

Si536812 Preliminary Rev. 0.411357CS0_C3ACS1_C4AI/O LVCMOS Input Clock Select/CKIN3 or CKIN4 Active Clock Indicator.Input: If manual clock selection i

Page 5

Si5368Preliminary Rev. 0.41 133435CKIN2+CKIN2–IMULTIClock Input 2.Differential input clock. This input can also be driven with a sin-gle-ended signal.

Page 6

Si536814 Preliminary Rev. 0.4155 INC I LVCMOS Coarse Latency Increment.A pulse on this pin increases the input to output device latency by 1/fOSC (app

Page 7 - 155.52 MHz in, 622.08 MHz out

Si5368Preliminary Rev. 0.41 1571 SDI I LVCMOS Serial Data In.In SPI microprocessor control mode (CMODE = 1), this pin functions as the serial data inp

Page 8 - C Control Mode)

Si536816 Preliminary Rev. 0.413. Register MapAll register bits that are not defined in this map should always be written with the specified Reset Val

Page 9 - 1. Functional Description

Si5368Preliminary Rev. 0.41 1723 LOS4_MSK LOS3_MSKLOS2_MSK LOS1_MSK LOSX_MSK24 ALIGN_MSK FOS4_MSK FOS3_MSKFOS2_MSK FOS1_MSK LOL_MSK25 N1_HS [2:0] NC1_

Page 10 - 2. Pin Descriptions: Si5368

Si536818 Preliminary Rev. 0.4154N34_[7:0]55CLKIN2RATE_[2:0] CLKIN1RATE[2:0]56CLKIN4RATE_[2:0] CLKIN3RATE[2:0]128CK4_ACTV_REGCK3_ACTV_REGCK2_ACTV_REGCK

Page 11 - Preliminary Rev. 0.41 11

Si5368Preliminary Rev. 0.41 194. Register DescriptionsReset value = 0001 0100 Register 0.BitD7D6D5D4D3D2D1D0Name FREE_RUNCKOUT_ALWAYS_ONCK_CONFIG_REG

Page 12 - 12 Preliminary Rev. 0.41

Si53682 Preliminary Rev. 0.41

Page 13 - Preliminary Rev. 0.41 13

Si536820 Preliminary Rev. 0.41Reset value = 1110 0100 Register 1.BitD7D6D5D4D3D2D1D0Name CK_PRIOR4 [1:0] CK_PRIOR3 [1:0] CK_PRIOR2 [1:0] CK_PRIOR1 [1:

Page 14 - 14 Preliminary Rev. 0.41

Si5368Preliminary Rev. 0.41 21Reset value = 0100 0010Reset value = 0000 0101 Register 2.BitD7D6D5D4D3D2D1D0Name BWSEL_REG [3:0] ReservedType R/W RBit

Page 15 - Preliminary Rev. 0.41 15

Si536822 Preliminary Rev. 0.41Reset value = 0001 0010Reset value = 1110 11014 SQ_ICAL SQ_ICAL.This bit determines if the output clocks will remain ena

Page 16 - 3. Register Map

Si5368Preliminary Rev. 0.41 23Bit Name Function7:6 ICMOS [1:0] ICMOS [1:0].When the output buffer is set to CMOS mode, these bits determine the output

Page 17 - Preliminary Rev. 0.41 17

Si536824 Preliminary Rev. 0.41Reset value = 0010 1100 Register 6.BitD7D6D5D4D3D2D1D0Name Reserved SLEEP SFOUT4_REG [2:0] SFOUT3_REG [2:0]Type RR/W R/W

Page 18 - 18 Preliminary Rev. 0.41

Si5368Preliminary Rev. 0.41 25Reset value = 0010 10102:0 SFOUT3_REG [2:0]SFOUT3_REG [2:0].Controls output signal format and disable for CKOUT3 output

Page 19 - 4. Register Descriptions

Si536826 Preliminary Rev. 0.41Reset value = 0000 00005:3 SFOUT5_REG [2:0]SFOUT5_REG [2:0]Controls output signal format and disable for CKOUT5 output b

Page 20 - 20 Preliminary Rev. 0.41

Si5368Preliminary Rev. 0.41 27Reset value = 1100 00005:4 HLOG_3 [1:0] HLOG_3 [1:0].00: Normal operation01: Holds CKOUT3 output at static logic 0. Entr

Page 21 - Preliminary Rev. 0.41 21

Si536828 Preliminary Rev. 0.41Reset value = 0000 0000 Register 10.BitD7D6D5D4D3D2D1D0Name Reserved DSBL5_REGReserved DSBL4_REGDSBL3_REGDSBL2_REGDSBL1_

Page 22 - 22 Preliminary Rev. 0.41

Si5368Preliminary Rev. 0.41 29Reset value = 0100 0000 Register 11.BitD7D6D5D4D3D2D1D0Name ALIGN_THR [2:0] ReservedPD_CK4 PD_CK3PD_CK2 PD_CK1Type R/W R

Page 23 - Preliminary Rev. 0.41 23

Si5368Preliminary Rev. 0.41 3TABLE OF CONTENTSSection Page1. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 24 - 24 Preliminary Rev. 0.41

Si536830 Preliminary Rev. 0.41Reset value = 1000 1000 Register 12.BitD7D6D5D4D3D2D1D0Name FPW_VALIDFSYNC_ALIGN_REGFSYNC_ALIGN_MODEFSYNC_SWTCH_REGFSKEW

Page 25 - Preliminary Rev. 0.41 25

Si5368Preliminary Rev. 0.41 31Reset value = 0000 0001Reset value = 0000 00002 FSYNC_SKEW [16:0]FSYNC_SKEW [16:0].Phase skew control for FSYNCOUT. The

Page 26 - 26 Preliminary Rev. 0.41

Si536832 Preliminary Rev. 0.41Reset value = 0000 0000Reset value = 0000 0000 Register 15.BitD7D6D5D4D3D2D1D0Name FSYNC_SKEW [7:0]Type R/WBit Name Func

Page 27 - Preliminary Rev. 0.41 27

Si5368Preliminary Rev. 0.41 33Reset value = 1000 0000Reset value = 0000 0000 Register 17.BitD7D6D5D4D3D2D1D0Name FLAT_VALIDFLAT [14:8]Type R/W R/WBit

Page 28 - 28 Preliminary Rev. 0.41

Si536834 Preliminary Rev. 0.41Reset value = 0010 1100 Register 19.BitD7D6D5D4D3D2D1D0Name FOS_EN FOS_THR [1:0] VALTIME [1:0] LOCKT [2:0]Type R/W R/W R

Page 29 - Preliminary Rev. 0.41 29

Si5368Preliminary Rev. 0.41 35Reset value = 0011 1100 Register 20.BitD7D6D5D4D3D2D1D0Name Reserved ALRMOUT_PINCK3_BAD_PINCK2_BAD_PINCK1_BAD_PINLOL_PIN

Page 30 - 30 Preliminary Rev. 0.41

Si536836 Preliminary Rev. 0.41Reset value = 1111 1111 Register 21.BitD7D6D5D4D3D2D1D0Name INCDEC_ PINReserved FSYNC_ALIGN_PINCK4_ACTV_PINCK3_ACTV_PINC

Page 31 - Preliminary Rev. 0.41 31

Si5368Preliminary Rev. 0.41 37Reset value = 1101 11111 CK1_ACTV_PINCK1_ACTV_PIN.The CK1_ACTV_REG status bit can be reflected to the CK1_ACTV output pi

Page 32 - 32 Preliminary Rev. 0.41

Si536838 Preliminary Rev. 0.41Reset value = 0001 11112 CK_BAD_ POLCK_BAD_POL.Sets the active polarity for the C1B, C2B, C3B, and ALRMOUT signals when

Page 33 - Preliminary Rev. 0.41 33

Si5368Preliminary Rev. 0.41 39Reset value = 0011 11111LOS1_MSKLOS1_MSK.Determines if a LOS on CKIN1 (LOS1_FLG) is used in the generation of an interru

Page 34 - 34 Preliminary Rev. 0.41

Si53684 Preliminary Rev. 0.41Table 1. Performance Specifications (VDD= 1.8 ±5%, 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 ºC)Parameter Symbol Test Cond

Page 35 - Preliminary Rev. 0.41 35

Si536840 Preliminary Rev. 0.41Reset value = 0010 00001 FOS1_MSK FOS1_MSK.Determines if the FOS1_FLG is used in the generation of an interrupt. Writes

Page 36 - 36 Preliminary Rev. 0.41

Si5368Preliminary Rev. 0.41 41Reset value = 0000 0000Reset value = 0011 0001 Register 26.BitD7D6D5D4D3D2D1D0Name NC1_LS [15:8]Type R/WBit Name Functio

Page 37 - Preliminary Rev. 0.41 37

Si536842 Preliminary Rev. 0.41Reset value = 0000 0000Reset value = 0000 0000 Register 28.BitD7D6D5D4D3D2D1D0Name Reserved NC2_LS [19:16]Type RR/WBit N

Page 38 - 38 Preliminary Rev. 0.41

Si5368Preliminary Rev. 0.41 43Reset value = 0011 0001Reset value = 0000 0000 Register 30.BitD7D6D5D4D3D2D1D0Name NC2_LS [7:0]Type R/WBit Name Function

Page 39 - Preliminary Rev. 0.41 39

Si536844 Preliminary Rev. 0.41Reset value = 0000 0000Reset value = 0011 0001 Register 32.BitD7D6D5D4D3D2D1D0Name NC3_LS [15:8]Type R/WBit Name Functio

Page 40 - 40 Preliminary Rev. 0.41

Si5368Preliminary Rev. 0.41 45Reset value = 0000 0000Reset value = 0000 0000 Register 34.BitD7D6D5D4D3D2D1D0Name Reserved NC4_LS [19:16]Type RR/WBit N

Page 41 - Preliminary Rev. 0.41 41

Si536846 Preliminary Rev. 0.41Reset value = 0011 0001Reset value = 0000 0000 Register 36.BitD7D6D5D4D3D2D1D0Name NC4_LS [7:0]Type R/WBit Name Function

Page 42 - 42 Preliminary Rev. 0.41

Si5368Preliminary Rev. 0.41 47Reset value = 0000 0000Reset value = 0011 0001 Register 38.BitD7D6D5D4D3D2D1D0Name NC5_LS [15:8]Type R/WBit Name Functio

Page 43 - Preliminary Rev. 0.41 43

Si536848 Preliminary Rev. 0.41Reset value = 1100 0000Reset value = 0000 0000 Register 40.BitD7D6D5D4D3D2D1D0Name N2_HS [2:0] Reserved N2_LS [19:16]Typ

Page 44 - 44 Preliminary Rev. 0.41

Si5368Preliminary Rev. 0.41 49Reset value = 1111 1001Reset value = 0000 0000 Register 42.BitD7D6D5D4D3D2D1D0Name N2_LS [7:0]Type R/WBit Name Function7

Page 45 - Preliminary Rev. 0.41 45

Si5368Preliminary Rev. 0.41 5Input Voltage Level Limits CKNVIN0—VDDVCommon Mode Voltage CKNVCM1.8 V ±5% 0.9 — 1.4 V2.5 V ±10% 1.0 — 1.7 V3.3 V ±10% 1.

Page 46 - 46 Preliminary Rev. 0.41

Si536850 Preliminary Rev. 0.41Reset value = 0000 0000Reset value = 0000 1001 Register 44.BitD7D6D5D4D3D2D1D0Name N31 [15:8]Type R/WBit Name Function7:

Page 47 - Preliminary Rev. 0.41 47

Si5368Preliminary Rev. 0.41 51Reset value = 0000 0000Reset value = 0000 0000 Register 46.BitD7D6D5D4D3D2D1D0Name Reserved N32_[18:16]Type RR/WBit Name

Page 48 - 48 Preliminary Rev. 0.41

Si536852 Preliminary Rev. 0.41Reset value = 0000 1001Reset value = 0000 0000 Register 48.BitD7D6D5D4D3D2D1D0Name N32_[7:0]Type R/WBit Name Function7:0

Page 49 - Preliminary Rev. 0.41 49

Si5368Preliminary Rev. 0.41 53Reset value = 0000 0000Reset value = 0000 1001 Register 50.BitD7D6D5D4D3D2D1D0Name N33_[15:8]Type R/WBit Name Function7:

Page 50 - 50 Preliminary Rev. 0.41

Si536854 Preliminary Rev. 0.41Reset value = 0000 0000Reset value = 0000 0000 Register 52.BitD7D6D5D4D3D2D1D0Name Reserved N34_[18:16]Type RR/WBit Name

Page 51 - Preliminary Rev. 0.41 51

Si5368Preliminary Rev. 0.41 55Reset value = 0000 1001Reset value = 0000 0000 Register 54.BitD7D6D5D4D3D2D1D0Name N34_[7:0]Type R/WBit Name Function7:0

Page 52 - 52 Preliminary Rev. 0.41

Si536856 Preliminary Rev. 0.41Reset value = 0000 0000 Register 56.BitD7D6D5D4D3D2D1D0Name Reserved CLKIN4RATE_[2:0] CLKIN3RATE[2:0]Type RR/W R/WBit Na

Page 53 - Preliminary Rev. 0.41 53

Si5368Preliminary Rev. 0.41 57Reset value = 0010 0000 Register 128.BitD7D6D5D4D3D2D1D0Name Reserved CK4_ACTV_REGCK3_ACTV_REGCK2_ACTV_REGCK1_ACTV_REGTy

Page 54 - 54 Preliminary Rev. 0.41

Si536858 Preliminary Rev. 0.41Reset value = 0001 1110 Register 129.BitD7D6D5D4D3D2D1D0Name ReservedLOS4_INT LOS3_INTLOS2_INT LOS1_INT LOSX_INTType R R

Page 55 - Preliminary Rev. 0.41 55

Si5368Preliminary Rev. 0.41 59Reset value = 0000 0001 Register 130.BitD7 D6D5D4D3D2 D1 D0Name CLAT-PROGRESSDIGHOLD-VALIDALIGN_INTFOS4_INT FOS3_INT FOS

Page 56 - 56 Preliminary Rev. 0.41

Si53686 Preliminary Rev. 0.41PackageThermal Resistance Junction to AmbientJAStill Air — 40 — ºC/WTable 2. Absolute Maximum RatingsParameter Symbol Va

Page 57 - Preliminary Rev. 0.41 57

Si536860 Preliminary Rev. 0.41Reset value = 0001 1111 Register 131.BitD7 D6D5D4D3D2 D1 D0Name Reserved LOS4_FLGLOS3_FLGLOS2_FLGLOS1_FLGLOSX_FLGType R

Page 58 - 58 Preliminary Rev. 0.41

Si5368Preliminary Rev. 0.41 61Reset value = 0000 0010 Register 132.BitD7D6D5D4D3D2D1D0Name Reserved ALIGN_FLGFOS4_FLG FOS3_FLG FOS2_FLG FOS1_FLG LOL_F

Page 59 - Preliminary Rev. 0.41 59

Si536862 Preliminary Rev. 0.41Reset value = 0000 00001LOL_FLGLOL_FLG.PLL Loss of Lock Flag.0: PLL locked1: Held version of LOL_INT. Generates active o

Page 60 - 60 Preliminary Rev. 0.41

Si5368Preliminary Rev. 0.41 63Reset value = 0000 0100Reset value = 0100 0010 Register 134.BitD7D6D5D4D3D2D1D0Name PARTNUM_RO [11:4]Type RBit Name Func

Page 61 - Preliminary Rev. 0.41 61

Si536864 Preliminary Rev. 0.41Reset value = 0000 0000 Register 136.BitD7D6D5D4D3D2D1D0Name RST_REG ICAL Reserved GRADE_RO [1:0]Type R/W R/W R RBit Nam

Page 62 - 62 Preliminary Rev. 0.41

Si5368Preliminary Rev. 0.41 65Reset value = 0000 1111 Register 138.BitD7D6D5D4D3D2D1D0Name Reserved LOS4_EN[1:1]LOS3_EN[1:1]LOS2_EN[1:1]LOS1_EN [1:1]T

Page 63 - Preliminary Rev. 0.41 63

Si536866 Preliminary Rev. 0.41Reset value = 1111 1111 Register 139.BitD7D6D5D4D3D2D1D0Name LOS4_EN [0:0]LOS3_EN [0:0]LOS2_EN [0:0]LOS1_EN [0:0]FOS4_EN

Page 64 - 64 Preliminary Rev. 0.41

Si5368Preliminary Rev. 0.41 67Reset value = 0000 00003FOS4_ENFOS4_EN.Enables FOS on a Per Channel Basis.0: Disable FOS monitoring.1: Enable FOS monito

Page 65 - Preliminary Rev. 0.41 65

Si536868 Preliminary Rev. 0.41Reset value = 0000 0001Reset value = 0000 0000Reset value = 0000 0000 Register 141.BitD7D6D5D4D3D2D1D0Name INDEPENDENTSK

Page 66 - 66 Preliminary Rev. 0.41

Si5368Preliminary Rev. 0.41 69Reset value = 0000 0000Reset value = 0001 0011 Register 144.BitD7D6D5D4D3D2D1D0Name INDEPENDENTSKEW5 [7:0]Type R/WBit Na

Page 67 - Preliminary Rev. 0.41 67

Si5368Preliminary Rev. 0.41 7Figure 1. Typical Phase Noise PlotJitter Band Jitter, RMSBrick Wall, 100 Hz to 100 MHz 1,279 fsSONET_OC48, 12 kHz to 20 M

Page 68 - 68 Preliminary Rev. 0.41

Si536870 Preliminary Rev. 0.41Table 5 lists all of the register locations that should be followed by an ICAL after their contents are changed.Table 4.

Page 69 - Preliminary Rev. 0.41 69

Si5368Preliminary Rev. 0.41 7134 NC4_LS37 NC5_LS40 N2_HS40 N2_LS43 N3146 N3249 N3351 N3455 CLKIN2RATE55 CLKIN1RATE56 CLKIN4RATE56 CLKIN3RATETable 5. R

Page 70 - 70 Preliminary Rev. 0.41

Si536872 Preliminary Rev. 0.415. Ordering GuideOrdering Part NumberOutput Clock Frequency RangePackage ROHS6, Pb-FreeTemperature RangeSi5368A-C-GQ 2

Page 71 - Preliminary Rev. 0.41 71

Si5368Preliminary Rev. 0.41 736. Package Outline: 100-Pin TQFPFigure 4 illustrates the package details for the Si5368. Table 6 lists the values for t

Page 72 - 5. Ordering Guide

Si536874 Preliminary Rev. 0.417. Recommended PCB LayoutFigure 5. PCB Land Pattern Diagram

Page 73

Si5368Preliminary Rev. 0.41 75Table 7. PCB Land Pattern DimensionsDimension MIN MAXe0.50 BSC.E 15.40 REF.D 15.40 REF.E2 3.90 4.10D2 3.90 4.10GE 13.90

Page 74 - 7. Recommended PCB Layout

Si536876 Preliminary Rev. 0.41DOCUMENT CHANGE LISTRevision 0.1 to Revision 0.2 Changed LVTTL to LVCMOS in Table 2, “Absolute Maximum Ratings,” on pag

Page 75

Si5368Preliminary Rev. 0.41 77NOTES:

Page 76 - DOCUMENT CHANGE LIST

Si536878 Preliminary Rev. 0.41CONTACT INFORMATIONSilicon Laboratories Inc.400 West Cesar ChavezAustin, TX 78701Tel: 1+(512) 416-8500Fax: 1+(512) 416-9

Page 77 - Preliminary Rev. 0.41 77

Si53688 Preliminary Rev. 0.41Figure 2. Si5368 Typical Application Circuit (I2C Control Mode)Figure 3. Si5368 Typical Application Circuit (SPI Control

Page 78 - CONTACT INFORMATION

Si5368Preliminary Rev. 0.41 91. Functional DescriptionThe Si5368 is a jitter-attenuating precision clock multiplierfor applications requiring sub 1 p