Silicon Laboratories SI5367 Manuel d'utilisateur télécharger pdf

Si5367

µP-PROGRAMMABLE PRECISION CLOCK MULTIPLIER

Features

Applications

Description

The Si5367 is a low jitter, precision clock multiplier for applications requiring clock

multiplication without jitter attenuation. The Si5367 accepts four clock inputs

ranging from 10 to 707 MHz and generates five frequency-multiplied clock outputs

ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device

provides virtually any frequency translation combination across this operating

range. The outputs are divided down separately from a common source. The

Si5367 input clock frequency and clock multiplication ratio are programmable

through an I

C or SPI interface. The Si5367 is based on Silicon Laboratories' 3rd-

generation DSPLL

technology, which provides any-frequency synthesis in a

highly integrated PLL solution that eliminates the need for external VCXO and

loop filter components. The DSPLL loop bandwidth is digitally programmable,

providing jitter performance optimization at the application level. Operating from a

single 1.8, 2.5, or 3.5 V supply, the Si5367 is ideal for providing clock

multiplication in high performance timing applications.

 Not recommended for new

designs. For alternatives, see the

Si533x family of products.

 Generates any frequency from

2 kHz to 945 MHz and select

frequencies to 1.4 GHz from an

input frequency of 10 to 710 MHz

 Low jitter clock outputs w/jitter

generation as low as 0.6 ps rms

(50 kHz–80 MHz)

 Integrated loop filter with

selectable loop bandwidth

(150 kHz to 1.3 MHz)

 Four clock inputs with manual or

automatically controlled

switching

 Five clock outputs with selectable

signal format (LVPECL, LVDS,

CML, CMOS)

 Support for ITU G.709 FEC ratios

(255/238, 255/237, 255/236)

 LOS alarm outputs

 I

C or SPI programmable

settings

 On-chip voltage regulator for

1.8 V ±5%, 2.5 V ±10%, or

3.5 V ±10% operation

 Small size: 14 x 14 mm 100-pin

TQFP

 Pb-free, RoHS compliant

 SONET/SDH OC-48/OC-192 STM-

16/STM-64 line cards

 GbE/10GbE, 1/2/4/8/10GFC line

cards

 ITU G.709 and custom FEC line

cards

 Wireless base stations

 Data converter clocking

 xDSL

 SONET/SDH + PDH clock synthesis

 Test and measurement

Ordering Information:

See page 73.

1 2 3 4 5 6 ... 79 80

Résumé du contenu

Page 1

Page 2 - Functional Block Diagram

Si536710 Rev. 1.0LVCMOS Input PinsMinimum Reset Pulse WidthtRSTMN1——µsReset to Microproces-sor Access ReadytREADY——10msInput Capacitance Cin—— 3 pFLVC

Page 3 - TABLE OF CONTENTS

Si5367Rev. 1.0 11PLL Performance(fin = fout = 622.08 MHz; BW = 120 Hz; LVPECL)Lock Time tLOCKMPStart of ICAL to of LOL — 35 1200 msClosed Loop Jitte

Page 4 - 1. Electrical Specifications

Si536712 Rev. 1.0SPI SpecificationsDuty Cycle, SCLK tDCSCLK = 10 MHz 40 — 60 %Cycle Time, SCLK tc100 — — nsRise Time, SCLK tr20–80% — — 25 nsFall Time

Page 5 - Table 2. DC Characteristics

Si5367Rev. 1.0 13Table 5. Jitter GenerationParameter SymbolTest Condition*Min Typ Max UnitMeasurement FilterJitter Gen OC-192JGEN 4–80 MHz — .23 — psr

Page 6

Si536714 Rev. 1.0Figure 3. Typical Phase Noise PlotTable 7. Absolute Maximum RatingsParameterSymbol Value UnitDC Supply Voltage VDD–0.5 to 3.8 VLVCMOS

Page 7

Si5367Rev. 1.0 152. Typical Application SchematicsFigure 4. Si5367 Typical Application Circuit (I2C Control Mode)Si5367CKIN1+CKIN1–INT_ALMCnBRSTCKOUT

Page 8

Si536716 Rev. 1.0Figure 5. Si5367 Typical Application Circuit (SPI Control Mode)Si5367CKIN1+CKIN1–INT_ALMCnBSPI InterfaceRSTCKOUT1+CKOUT1–VDDGNDResetI

Page 9 - Table 3. AC Characteristics

Si5367Rev. 1.0 173. Functional DescriptionThe Si5367 is a low jitter, precision clock multiplier forapplications requiring clock multiplication with

Page 10 - = –40 to 85 °C)

Si536718 Rev. 1.04. Register MapAll register bits that are not defined in this map should always be written with the specified Reset Values. Thewriti

Page 11 - — –132 — dBc/Hz

Si5367Rev. 1.0 1939 NC5_LS [7:0]40 N2_LS [19:16]41 N2_LS [15:8]42 N2_LS [7:0]43 N31_ [18:16]44 N31_[15:8]45 N31_ [7:0]46 N32_ [18:16]47 N31_ [15:8]48

Page 12 - 12 Rev. 1.0

Si53672 Rev. 1.0Functional Block DiagramI2C/SPI PortClock SelectCKOUT2CKIN1CKOUT1CKIN2ControlCKIN3CKIN4CKOUT4CKOUT5VDD (1.8 or 2.5 V)GND÷ N32÷ N31DSP

Page 13 - Table 5. Jitter Generation

Si536720 Rev. 1.05. Register DescriptionsReset value = 0001 0100 Register 0.BitD7D6 D5 D4D3D2 D1 D0Name CKOUT_ALWAYS_ON BYPASS_REGType RR R/W RRR R/W

Page 14 - 14 Rev. 1.0

Si5367Rev. 1.0 21Reset value = 1110 0100 Register 1.BitD7D6D5D4D3D2D1D0Name CK_PRIOR4 [1:0] CK_PRIOR3 [1:0] CK_PRIOR2 [1:0] CK_PRIOR1 [1:0]Type R/W R/

Page 15 - C Control Mode)

Si536722 Rev. 1.0Reset value = 0100 0010Reset value = 0000 0101 Register 2.BitD7D6D5D4D3D2D1D0Name BWSEL_REG [3:0]Type R/W R R R RBit Name Function7:4

Page 16 - 16 Rev. 1.0

Si5367Rev. 1.0 23Reset value = 0001 0010 Register 4.BitD7D6D5D4D3D2D1D0Name AUTOSEL_REG [1:0]Type R/W RRRRRRBit Name Function7:6 AUTOSEL_REG [1:0] AUT

Page 17 - Rev. 1.0 17

Si536724 Rev. 1.0Reset value = 1110 1101 Register 5.BitD7D6D5D4D3D2D1D0Name ICMOS [1:0] SFOUT2_REG [2:0] SFOUT1_REG [2:0]Type R/W R/W R/WBit Name Func

Page 18 - 18 Rev. 1.0

Si5367Rev. 1.0 25Reset value = 0010 1100 Register 6.BitD7D6D5D4D3D2D1D0Name SFOUT4_REG [2:0] SFOUT3_REG [2:0]Type RR R/W R/WBit Name Function7:6 Reser

Page 19 - Rev. 1.0 19

Si536726 Rev. 1.0Reset value = 0010 1010 Register 7.BitD7D6D5D4D3D2D1D0Name SFOUT5_REG [2:0] FOSREFSEL [2:0]Type RR R/W R/WBit Name Function7:6 Reserv

Page 20 - 20 Rev. 1.0

Si5367Rev. 1.0 27Reset value = 0000 0000 Register 8.BitD7D6D5D4D3D2D1D0Name HLOG_4[1:0] HLOG_3[1:0] HLOG_2[1:0] HLOG_1[1:0]Type R/W R/W R/W R/WBit Nam

Page 21 - Rev. 1.0 21

Si536728 Rev. 1.0Reset value = 1100 0000 Register 9.BitD7D6D5D4D3D2D1D0Name HLOG_5 [1:0]Type RRRRRR R/WBit Name Function7:2 Reserved 1:0 HLOG_5 [1:0

Page 22 - 22 Rev. 1.0

Si5367Rev. 1.0 29Reset value = 0000 0000 Register 10.BitD7D6D5D4D3D2D1D0Name DSBL5_REG DSBL4_REG DSBL3_REG DSBL2_REG DSBL1_REGType RR R/W R R/W R/W R

Page 23 - Rev. 1.0 23

Si5367Rev. 1.0 3TABLE OF CONTENTSSection Page1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 24 - 24 Rev. 1.0

Si536730 Rev. 1.0Reset value = 0100 0000 Register 11.BitD7D6D5D4D3D2D1D0NamePD_CK4 PD_CK3PD_CK2 PD_CK1Type RRRRR/WR/WR/WR/WBit Name Function7:4 Reserv

Page 25 - Rev. 1.0 25

Si5367Rev. 1.0 31Reset value = 0010 1100 Register 19.BitD7D6D5D4D3D2D1D0Name FOS_EN FOS_THR [1:0] VALTIME [1:0]Type R/W R/W R/W R R RBit Name Function

Page 26 - 26 Rev. 1.0

Si536732 Rev. 1.0Reset value = 0011 1100 Register 20.BitD7D6D5 D4 D3 D2 D1 D0Name CK3_BAD_PIN CK2_BAD_PIN CK1_BAD_PIN INT_PINType R R R R/W R/W R/W R

Page 27 - Rev. 1.0 27

Si5367Rev. 1.0 33Reset value = 1111 1111 Register 21.Bit D7 D6 D5 D4 D3 D2 D1 D0Name CK4_ACTV_PIN* CK3_ACTV_PIN* CK2_ACTV_PIN* CK1_ACTV_PIN* CKSEL_ PI

Page 28 - 28 Rev. 1.0

Si536734 Rev. 1.0Reset value = 1101 1111 Register 22.Bit D7 D6 D5 D4 D3 D2 D1 D0Name FSYNCOUT_POL CK_ACTV_POL CK_BAD_ POL INT_POLType R/W R/W R R/W R/

Page 29 - Rev. 1.0 29

Si5367Rev. 1.0 35Reset value = 0001 1111 Register 23.BitD7D6D5 D4 D3 D2 D1 D0Name LOS4_MSK LOS3_MSK LOS2_ MSK LOS1_ MSKType R R R R/W R/W R/W R/W RBit

Page 30 - 30 Rev. 1.0

Si536736 Rev. 1.0Reset value = 0011 1111 Register 24.BitD7D6D5D4D3D2D1D0Name FOS4_MSK FOS3_MSK FOS2_MSK FOS1_MSKType RRRR/WR/WR/WR/WR/WBit Name Functi

Page 31 - Rev. 1.0 31

Si5367Rev. 1.0 37Reset value = 0010 0000Reset value = 0000 0000 Register 25.BitD7D6D5D4D3D2D1D0Name N1_HS [2:0] NC1_LS [19:16]Type R/W R R/WBit Name F

Page 32 - 32 Rev. 1.0

Si536738 Rev. 1.0Reset value = 0011 0001Reset value = 0000 0000 Register 27.BitD7D6D5D4D3D2D1D0Name NC1_LS [7:0]Type R/WBit Name Function7:0 NC1_LS [7

Page 33 - Rev. 1.0 33

Si5367Rev. 1.0 39Reset value = 0000 0000Reset value = 0011 0001 Register 29.BitD7D6D5D4D3D2D1D0Name NC2_LS [15:8]Type R/WBit Name Function7:0 NC2_LS [

Page 34 - 34 Rev. 1.0

Si53674 Rev. 1.01. Electrical SpecificationsFigure 1. Differential Voltage CharacteristicsFigure 2. Rise/Fall Time CharacteristicsTable 1. Recommende

Page 35 - Rev. 1.0 35

Si536740 Rev. 1.0Reset value = 0000 0000Reset value = 0000 0000 Register 31.BitD7D6D5D4D3D2D1D0Name NC3_LS [19:16]Type RRRR R/WBit Name Function7:4 Re

Page 36 - 36 Rev. 1.0

Si5367Rev. 1.0 41Reset value = 0011 0001Reset value = 0000 0000 Register 33.BitD7D6D5D4D3D2D1D0Name NC3_LS [7:0]Type R/WBit Name Function7:0 NC3_LS [7

Page 37 - Rev. 1.0 37

Si536742 Rev. 1.0Reset value = 0000 0000Reset value = 0011 0001 Register 35.BitD7D6D5D4D3D2D1D0Name NC4_LS [15:8]Type R/WBit Name Function7:0 NC4_LS [

Page 38 - 38 Rev. 1.0

Si5367Rev. 1.0 43Reset value = 0000 0000Reset value = 0000 0000 Register 37.BitD7D6D5D4D3D2D1D0Name NC5_LS [19:16]Type RRRR R/WBit Name Function7:4 Re

Page 39 - Rev. 1.0 39

Si536744 Rev. 1.0Reset value = 0011 0001Reset value = 1100 0000 Register 39.BitD7D6D5D4D3D2D1D0Name NC5_LS [7:0]Type R/WBit Name Function7:0 NC5_LS [7

Page 40 - 40 Rev. 1.0

Si5367Rev. 1.0 45Reset value = 0000 0000Reset value = 1111 1001 Register 41.BitD7D6D5D4D3D2D1D0Name N2_LS [15:8]Type R/WBit Name Function7:0 N2_LS [15

Page 41 - Rev. 1.0 41

Si536746 Rev. 1.0Reset value = 0000 0000Reset value = 0000 0000 Register 43.BitD7D6D5D4D3D2D1D0Name N31 [18:16]Type RRRRR R/WBit Name Function7:3 Rese

Page 42 - 42 Rev. 1.0

Si5367Rev. 1.0 47Reset value = 0000 1001Reset value = 0000 0000 Register 45.BitD7D6D5D4D3D2D1D0Name N31 [7:0]Type R/WBit Name Function7:0 N31 [7:0] N3

Page 43 - Rev. 1.0 43

Si536748 Rev. 1.0Reset value = 0000 0000Reset value = 0000 1001 Register 47.BitD7D6D5D4D3D2D1D0Name N32_[15:8]Type R/WBit Name Function7:0 N32_[15:8]

Page 44 - 44 Rev. 1.0

Si5367Rev. 1.0 49Reset value = 0000 0000Reset value = 0000 0000 Register 49.BitD7D6D5D4D3D2D1D0Name N33_[18:16]Type RRRRR R/WBit Name Function18:0 N33

Page 45 - Rev. 1.0 45

Si5367Rev. 1.0 5Table 2. DC Characteristics(VDD= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)Parameter Symbol Test Condition Min Typ Max UnitS

Page 46 - 46 Rev. 1.0

Si536750 Rev. 1.0Reset value = 0000 1001Reset value = 0000 0000 Register 51.BitD7D6D5D4D3D2D1D0Name N33_[7:0]Type R/WBit Name Function7:0 N33_[7:0] N3

Page 47 - Rev. 1.0 47

Si5367Rev. 1.0 51Reset value = 0000 0000Reset value = 0000 1001 Register 53.BitD7D6D5D4D3D2D1D0Name N34_[15:8]Type R/WBit Name Function7:0 N34_[15:8]

Page 48 - 48 Rev. 1.0

Si536752 Rev. 1.0Reset value = 0000 0000 Register 55.BitD7D6D5D4D3D2D1D0Name CLKIN2RATE_[5:3] CLKIN1RATE[2:0]Type RR R/W R/WBit Name Function7:6 Reser

Page 49 - Rev. 1.0 49

Si5367Rev. 1.0 53Reset value = 0000 0000 Register 56.BitD7D6D5D4D3D2D1D0Name CLKIN4RATE_[5:3] CLKIN3RATE[2:0]Type RR R/W R/WBit Name Function7:6 Reser

Page 50 - 50 Rev. 1.0

Si536754 Rev. 1.0Reset value = 0010 0000 Register 128.Bit D7D6D5D4 D3 D2 D1 D0Name CK4_ACTV_REG CK3_ACTV_REG CK2_ACTV_REG CK1_ACTV_REGType RRRR R R R

Page 51 - Rev. 1.0 51

Si5367Rev. 1.0 55Reset value = 0001 1110 Register 129.BitD7D6D5D4D3D2D1D0NameLOS4_INT LOS3_INTLOS2_INT LOS1_INTType RRRRRRRRBit Name Function7:5 Reser

Page 52 - 52 Rev. 1.0

Si536756 Rev. 1.0Reset value = 0000 0001 Register 130.BitD7 D6D5D4D3D2 D1 D0Name FOS4_INT FOS3_INT FOS2_INT FOS1_INTType RRRRRRRRBit Name Function7:5

Page 53 - Rev. 1.0 53

Si5367Rev. 1.0 57Reset value = 0001 1111 Register 131.BitD7D6D5 D4 D3 D2 D1 D0Name LOS4_FLG LOS3_FLG LOS2_FLG LOS1_FLGType R R R R/W R/W R/W R/W RBit

Page 54 - 54 Rev. 1.0

Si536758 Rev. 1.0Reset value = 0000 0010 Register 132.BitD7D6 D5D4D3D2D1D0Name FOS4_FLG FOS3_FLG FOS2_FLG FOS1_FLGType R R R/W R/W R/W R/W R/W RBit Na

Page 55 - Rev. 1.0 55

Si5367Rev. 1.0 59Reset value = 0000 0100Reset value = 0100 0010 Register 134.BitD7D6D5D4D3D2D1D0Name PARTNUM_RO [11:4]Type RBit Name Function7:0 PARTN

Page 56 - 56 Rev. 1.0

Si53676 Rev. 1.0Common Mode CKOVCMLVPECL 100  load line-to-lineVDD –1.42 — VDD –1.25 VDifferential Output SwingCKOVDLVPECL 100  load line-to-line1.1

Page 57 - Rev. 1.0 57

Si536760 Rev. 1.0Reset value = 0000 0000 Register 136.BitD7D6D5D4D3D2D1D0Name RST_REG ICALType R/WR/WRRRRRRBit Name Function7 RST_REG RST_REG.Internal

Page 58 - 58 Rev. 1.0

Si5367Rev. 1.0 61Reset value = 0000 1111 Register 138.BitD7D6D5D4 D3 D2 D1 D0Name LOS4_EN[1:1] LOS3_EN[1:1] LOS2_EN[1:1] LOS1_EN [1:1]Type RRRR R/W R/

Page 59 - Rev. 1.0 59

Si536762 Rev. 1.0Reset value = 1111 1111 Register 139.Bit D7 D6 D5 D4 D3 D2 D1 D0Name LOS4_EN [0:0] LOS3_EN [0:0] LOS2_EN [0:0] LOS1_EN [0:0] FOS4_EN

Page 60 - 60 Rev. 1.0

Si5367Rev. 1.0 63Reset value = 0000 00003FOS4_ENFOS4_EN.Enables FOS on a Per Channel Basis.0: Disable FOS monitoring.1: Enable FOS monitoring.2FOS3_EN

Page 61 - Rev. 1.0 61

Si536764 Rev. 1.0Reset value = 0000 0001Reset value = 0000 0000Reset value = 0000 0000 Register 141.BitD7D6D5D4D3D2D1D0Name INDEPENDENTSKEW2 [7:0]Type

Page 62 - 62 Rev. 1.0

Si5367Rev. 1.0 65Reset value = 0000 0000Table 10 lists all of the register locations that should be followed by an ICAL after their contents are chang

Page 63 - Rev. 1.0 63

Si536766 Rev. 1.0Table 10. Register Locations Requiring ICALAddr Register0 BYPASS_REG0 CKOUT_ALWAYS_ON1 CK_PRIOR41 CK_PRIOR31 CK_PRIOR21 CK_PRIOR12 BW

Page 64 - 64 Rev. 1.0

Si5367Rev. 1.0 676. Pin Descriptions: Si53671234567891011121314151648474645444342414039383736353433313029282726 3264616263575859605051525354555649NCG

Page 65 - Rev. 1.0 65

Si536768 Rev. 1.0Table 11. Si5367 Pin Descriptions Pin # Pin Name I/O Signal Level Description1, 2, 4, 17, 20, 22, 23, 24, 25, 37, 47, 48, 49, 50, 51,

Page 66 - 66 Rev. 1.0

Si5367Rev. 1.0 6911 C3B O LVCMOS CKIN3 Invalid Indicator.This pin performs the CK3_BAD function if CK3_BAD_PIN= 1 and is tristated if CK3_BAD_PIN =0.

Page 67 - 6. Pin Descriptions: Si5367

Si5367Rev. 1.0 7Output Drive Current (CMOS driving into CKOVOL for output low or CKOVOH for output high. CKOUT+ and CKOUT– shorted externally)CKOIOICM

Page 68 - 68 Rev. 1.0

Si536770 Rev. 1.02930CKIN4+CKIN4–IMULTIClock Input 4.Differential clock input. This input can also be driven with a single-ended signal. CKIN4 serves

Page 69 - Rev. 1.0 69

Si5367Rev. 1.0 7170 A2_SS ILVCMOSSerial Port Address/Slave Select.In I2C microprocessor control mode (CMODE = 0), this pin functions as a hardware con

Page 70 - 70 Rev. 1.0

Si536772 Rev. 1.09798CKOUT4–CKOUT4+OMULTIClock Output 4.Differential clock output. Output signal format is selected by SFOUT4_REG register bits. Outpu

Page 71 - Rev. 1.0 71

Si5367Rev. 1.0 737. Ordering GuideOrdering Part NumberOutput Clock Frequency RangePackage ROHS6, Pb-FreeTemperature RangeSi5367A-C-GQ* .002–945 MHz97

Page 72 - 72 Rev. 1.0

Si536774 Rev. 1.08. Package Outline: 100-Pin TQFPFigure 6 illustrates the package details for the Si5367. Table 12 lists the values for the dimension

Page 73 - Rev. 1.0 73

Si5367Rev. 1.0 759. PCB Land PatternFigure 7. PCB Land Pattern Diagram

Page 74

Si536776 Rev. 1.0Table 13. PCB Land Pattern DimensionsDimension MIN MAXe0.50 BSC.E 15.40 REF.D 15.40 REF.E2 3.90 4.10D2 3.90 4.10GE 13.90 —GD 13.90 —X

Page 75 - Rev. 1.0 75

Si5367Rev. 1.0 7710. Top Marking10.1. Si5367 Top Marking10.2. Top Marking ExplanationMark Method: LaserLogo Size: 9.2 x 3.1 mmCenter-JustifiedFont

Page 76

Si536778 Rev. 1.0DOCUMENT CHANGE LISTRevision 0.1 to Revision 0.2 Changed LVTTL to LVCMOS in Absolute Maximum Ratings table. Updated “6. Pin Descrip

Page 77 - Rev. 1.0 77

Si5367Rev. 1.0 79NOTES:

Page 78 - Changed pin 16 to ground

Si53678 Rev. 1.03-Level Input Pins6Input Voltage Low VILL— — 0.15 x VDDVInput Voltage Mid VIMM0.45 x VDD—0.55xVDDVInput Voltage High VIHH0.85 x VDD——V

Page 79 - Rev. 1.0 79

Si536780 Rev. 1.0CONTACT INFORMATIONSilicon Laboratories Inc.400 West Cesar ChavezAustin, TX 78701Tel: 1+(512) 416-8500Fax: 1+(512) 416-9669Toll Free:

Page 80 - CONTACT INFORMATION

Si5367Rev. 1.0 9Table 3. AC Characteristics(VDD= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)Parameter Symbol Test Condition Min Typ Max UnitC