Silicon Laboratories SI5316 Manuel d'utilisateur

Rev. 0.4 4/08 Copyright © 2008 by Silicon Laboratories Si5316Si5316PRECISION CLOCK JITTER ATTENUATORDescriptionThe Si5316 is a low jitter, precision j

Si531610 Rev. 0.43330SFOUT0SFOUT1I 3-Level Signal Format Select.Three level inputs that select the output signal format (common mode voltage and diffe

Si5316Rev. 0.4 113. Ordering GuideOrdering Part Number Package ROHS6, Pb-Free Temperature RangeSi5316-C-GM 36-Lead 6 x 6 mm QFN Yes –40 to 85 °C

Si531612 Rev. 0.44. Package Outline: 36-Lead QFNFigure 3 illustrates the package details for the Si5316. Table 4 lists the values for the dimensions

Si5316Rev. 0.4 135. Recommended PCB LayoutFigure 4. PCB Land Pattern Diagram

Si531614 Rev. 0.4Table 5. PCB Land Pattern DimensionsDimension MIN MAXe 0.50 BSC.E5.42 REF.D5.42 REF.E2 4.00 4.20D2 4.00 4.20GE 4.53 —GD 4.53 —X — 0.2

Si5316Rev. 0.4 15DOCUMENT CHANGE LISTRevision 0.23 to 0.24 Changed LVTTL to LVCMOS in Table 2, “Absolute Maximum Ratings,” on page 3. Added Figure 1

Si531616 Rev. 0.4CONTACT INFORMATIONSilicon Laboratories Inc.400 West Cesar ChavezAustin, TX 78701Tel: 1+(512) 416-8500Fax: 1+(512) 416-9669Toll Free:

Si53162 Rev. 0.4Table 1. Performance Specifications1(VDD= 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA= –40 to 85 ºC)Parameter Symbol Test Condition Min Typ M

Si5316Rev. 0.4 3Jitter Transfer JPK—0.050.1dBExternal Reference Jitter TransferJPKEXTN— 30 — kHzPhase NoisefIN=fOUT=622.08CKOPN100 Hz offset — –65 –50

Si53164 Rev. 0.4Figure 1. Typical Phase Noise PlotJitter Band Jitter, RMSBrick Wall, 100 Hz to 100 MHz 1,279 fsSONET_OC48, 12 kHz to 20 MHz 315 fsSONE

Si5316Rev. 0.4 5Figure 2. Si5316 Typical Application CircuitSi5316CSCK1DIV2C1BC2BCK2DIV2FRQSEL[1:0]2LOLBWSEL[1:0]2SFOUT[1:0]2RATE2DBL_BY2RSTXAXBCKOUT+

Si53166 Rev. 0.41. Functional DescriptionThe Si5316 is a precision jitter attenuator for high-speedcommunication systems, including OC-48/STM-16, OC-

Si5316Rev. 0.4 72. Pin Descriptions: Si5316Table 3. Si5316 Pin Descriptions Pin # Pin Name I/O Signal Level Description1RSTILVCMOSExternal Reset.Acti

Si53168 Rev. 0.476XBXAIAnalogExternal Crystal or Reference Clock.External crystal should be connected to these pins to use internal oscillator based r

Si5316Rev. 0.4 92322BWSEL1BWSEL0I 3-Level Bandwidth Select.Three level inputs that select the DSPLL closed loop bandwidth. Detailed operations and tim